Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.

An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

A semiconductor package includes a semiconductor chip including a second bonding insulating layer surrounding at least a portion of each of a first bonding pad structure and a second bonding pad structure, in which the first bonding pad structure includes a first contact portion, a first bonding pad, and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, the second bonding pad structure includes a second contact portion, a second bonding pad, and a second seed layer disposed between the second bonding pad and the second contact portion and extending in the first direction, and the second bonding insulating layer is in contact with a side surface of each of the first and second seed layers and the first and second bonding pads.

Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.

A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

A display device includes a display panel including panel pads adjacent to the side surface of a display panel; connection pads disposed on the side surface of the display panel and connected to the panel pads; and a circuit board disposed on the side surface of the display panel and including lead signal lines directly bonded to the connection pads, wherein the connection pads include a first connection pad, a second connection pad disposed on the first connection pad, and a third connection pad disposed on the second connection pad, and the first connection pad is in contact with corresponding one of the panel pads, and the third connection pad is directly bonded to corresponding one of the lead signal lines.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.