A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

Provided is a method for manufacturing a conductive pillar capable of bonding a substrate and a bonding member with high bonding strength via a bonding layer without employing an electroplating method, and a method for manufacturing a bonded structure by employing this method. A method for manufacturing a conductive pillar 1 includes, in sequence, the steps of forming a resist layer 16 on a substrate 11 provided with an electrode pad 13, the resist layer 16 including an opening portion 16a on the electrode pad 13, forming a thin Cu film 17 by sputtering or evaporating Cu on a surface of the substrate 11 provided with the resist layer 16 including the opening portion 16a, filling the opening portion 16a with a fine particle copper paste 12c, and sintering the fine particle copper paste 12c by heating the substrate 11 filled with the fine particle copper paste 12c.

A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electrically conductive.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.