In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.

A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

A light emitting device for a display including a first LED stack configured to generate light having a first peak wavelength, a second LED stack disposed under the first LED stack, and configured to generate light having a second peak wavelength, a third LED stack disposed under the second LED stack, and configured to generate light having a third peak wavelength; and a floating reflection layer disposed over the first LED stack, in which the first peak wavelength is longer than the second and third peak wavelengths, the first LED stack has a roughened surface to increase the luminous intensity of the light generated in the first LED stack entering the second LED stack, and the floating reflection layer has a high reflectance of 80% or more over light having the first peak wavelength.

Provided is a method for manufacturing a conductive pillar capable of bonding a substrate and a bonding member with high bonding strength via a bonding layer without employing an electroplating method, and a method for manufacturing a bonded structure by employing this method. A method for manufacturing a conductive pillar 1 includes, in sequence, the steps of forming a resist layer 16 on a substrate 11 provided with an electrode pad 13, the resist layer 16 including an opening portion 16a on the electrode pad 13, forming a thin Cu film 17 by sputtering or evaporating Cu on a surface of the substrate 11 provided with the resist layer 16 including the opening portion 16a, filling the opening portion 16a with a fine particle copper paste 12c, and sintering the fine particle copper paste 12c by heating the substrate 11 filled with the fine particle copper paste 12c.

A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electrically conductive.

A semiconductor device having a substrate, a semiconductor chip, and a plurality of electrode terminals is provided. The substrate has first and second principal surfaces. The semiconductor chip is disposed on the first principal surface. The electrode terminals are disposed on the second principal surface. The substrate has a via interconnection near a position at which an outer edge line of the semiconductor chip intersects an outer outline of the electrode terminal farthest from a center of the substrate, the electrode terminal farthest from the center of the substrate being among the plurality of electrode terminals overlapping the outer edge line in a predetermined condition as seen through the substrate of the semiconductor device from a direction perpendicular to the first principal surface, the via interconnection connecting a first interconnection layer on a first principal surface-side to a second interconnection layer on a second principal surface-side.

Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.

Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

A semiconductor package includes: a first redistribution layer; a first semiconductor chip including a first side and a second side, wherein the first side faces the first redistribution layer; a first sealing material covering the second side of the first semiconductor chip and having a first filler content; a second sealing material formed on the first sealing material and having a second filler content lower than the first filler content; and a second redistribution layer disposed on the second sealing material.