A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.

A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.

Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.