Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Provided is an electronic device including a substrate, a first metal layer, an electronic component, a cover layer, and an adhesive layer. The first metal layer is formed on the substrate. The electronic component is disposed on the substrate and electrically connected to the first metal layer. The adhesive layer is adhered to the substrate and the cover layer.

Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.

A bonding structure is provided, including a first substrate; a second substrate disposed opposite the first substrate; a first bonding layer disposed on the first substrate; a second bonding layer disposed on the second substrate and opposite the first bonding layer; and a silver feature disposed between the first bonding layer and the second bonding layer. The silver feature includes a silver nano-twinned structure including parallel twin boundaries. The silver nano-twinned structure includes 90% or more [111] crystal orientation. A method for forming a bonding structure is also provided. Each of steps of forming a first silver feature and second silver feature includes sputtering or evaporation coating. Negative bias ion bombardment is applied to the first silver feature and second silver feature during sputtering or evaporation.

A semiconductor package includes a package substrate, an interposer on the package substrate, a lower molding layer on the package substrate and surrounding the interposer, a first semiconductor chip on the lower molding layer, a chip connection terminal between the first semiconductor chip and the package substrate and surrounded by the lower molding layer, a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip, interposer connection terminals that connect the first and second semiconductor chips to the interposer, and an upper molding layer on the lower molding layer and surrounding the first and second semiconductor chips.

The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

A display is provided. The display includes a first substrate comprising a plurality of electrode pads disposed on a front surface, a plurality of solder members disposed on a rear surface, and a plurality of wiring members electrically connecting the plurality of electrode pads and the plurality of solder members, respectively, a plurality of light-emitting elements electrically connected to each of the plurality of electrode pads, and constituting pixels of two columns, and a second substrate comprising a thin film transistor (TFT) layer disposed on a rear side of the first substrate and electrically connected to the plurality of solder members to control driving of the plurality of light-emitting elements, and the first substrate may include a first region in which pixels of a first column are disposed, a second region in which pixels of a second column are disposed, and a third region disposed between the first region and the second region, the plurality of wiring members may be disposed on the first region and the second region among the front surface of the first substrate.

A semiconductor package including a first substrate including a first bump pad and a filling compensation film (FCF) around the first bump pad; a second substrate facing the first substrate and including a second bump pad; a bump structure (BS) in contact with the first bump pad and the second bump pad; and a non-conductive film (NCF) surrounding the BS and between the first substrate and the second substrate, wherein the NCF covers an upper surface and an edge of the FCF.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.