A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.

A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.

Disclosed are a system-on-chip integrated packaging structure, a manufacturing method therefor and a three-dimensional stacked device. The system-on-chip integrated packaging structure includes: a substrate, a chip, a first electrical connection structure and a second electrical connection structure. A front surface of the substrate is provided with a recess and a via welding pad, and a back surface of the substrate is provided with a conductive via extending to the via welding pad. The chip is embedded in the recess, and a chip welding pad is disposed on a surface of the chip away from a bottom surface of the recess. Different chips may be electrically connected by means of the first electrical connection structure and the second electrical connection structure, which is conducive to form a three-dimensional stacked structure with high-density interconnection, miniaturized packaging and thinning.

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

A method for producing a document structure, wherein the method includes producing a chip structure by forming a cavity in a carrier having a top side and an under side, picking up a chip having at least one chip contact and a redistribution layer (RDL) connected to the at least one chip contact by means of a picking-up device detaching the chip from an auxiliary carrier, wherein the chip bears on the auxiliary carrier by way of the RDL, wherein the chip is lifted up from the auxiliary carrier by means of pressure being exerted on the RDL, wherein the lifted-up chip is picked up and inserted into the cavity, and wherein the RDL is oriented on the top side of the carrier, fixing the chip in the cavity by means of an adhesive, electrically conductively connecting the at least one chip contact of the RDL to an electrically conductive region of the carrier by means of an electrically conductive material, and embedding the carrier between a first paper layer and a second paper layer.

A display device includes: a substrate; a plurality of pixel columns on the substrate, each of the plurality of pixel columns including a plurality of pixel groups each including a first pixel and a second pixel arranged along a first direction; and a bank enclosing a perimeter of each of the plurality of pixel groups, the bank including a first opening corresponding to each of the plurality of pixel groups, and a second opening located between two pixel groups adjacent to each other in the first direction among the plurality of pixel groups.