Patent classifications
H01L24/24
Electronic device module
An electronic device module includes: a substrate; a sealing portion disposed on the substrate; at least one electronic device mounted on the substrate and embedded in the sealing portion; and a roof wiring at least partially disposed on a surface of the sealing portion and electrically connecting the substrate to the at least one electronic device or electrically connecting electronic devices, among the at least one electronic device, to each other. The roof wiring includes: a surface wiring disposed on one surface of the sealing portion; and at least one post wiring connecting the surface wiring to the substrate or to the at least one electronic device, and wherein at least a portion of a circumferential surface of the at least one post wiring is bonded to the surface wiring.
LIGHT EMITTING DEVICE, DISPLAY APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME
A light emitting device may be a bar-type light emitting device and include a n-GaN semiconductor layer, a p-GaN semiconductor layer spaced apart from the n-GaN semiconductor layer, an active layer arranged between the n-GaN semiconductor layer and the p-GaN semiconductor layer, and a strain relaxing layer including indium clusters and voids.
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Disclosed are semiconductor packages and their fabricating methods. The method includes preparing a semiconductor chip with a pillar pattern on a bottom surface thereof, placing the semiconductor chip side by side with a connection substrate with a conductive pad on a bottom surface thereof, forming a molding layer on the bottom surfaces of the connection substrate and the semiconductor chip to cover the pillar pattern and the conductive pad, forming a first redistribution substrate on top surfaces of the connection substrate, the semiconductor chip, and the molding layer and directly in physical contact with the top surface of the semiconductor chip, and performing a grinding process on a bottom surface of the molding layer to expose the pillar pattern and the conductive pad. An outer sidewall of the connection substrate is vertically aligned with that of the first redistribution substrate.
MICROELECTRONIC ASSEMBLIES HAVING TOPSIDE POWER DELIVERY STRUCTURES
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the insulating material including a second conductive pathway electrically coupled to the TSV; and a second microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the first microelectronic component.
MICROELECTRONIC ASSEMBLIES HAVING TOPSIDE POWER DELIVERY STRUCTURES
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.
Wireless transmission module and manufacturing method
A wireless transmission module, chips, a passive component, and a coil are integrated into an integral structure, so that an integration level of the wireless transmission module is improved. In addition, the integral structure can effectively implement independence of the module, and the independent module can be flexibly arranged inside structural design of an electronic device, and does not need to be disposed on a mainboard of the electronic device. Only an input terminal of the wireless transmission module needs to be retained on the mainboard of the electronic device. In addition, the integral structure can further effectively increase a capability of a product for working continuously and normally in an extremely harsh scenario, and improve product reliability. In addition, in the structure of the wireless transmission module, the chips and the coil are integrated, and signal transmission paths between the chips and the coil are relatively short.
Method of forming integrated circuit packages with mechanical braces
In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.
Semiconductor package including passive device embedded therein and method of manufacturing the same
A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.
Method and apparatus to increase radar range
An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.
Semiconductor device
A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.