A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.

A display device includes conductive layers including wires and conductive patterns in a display area and a pad area, a via layer on the conductive layers, a first electrode and a second electrode on the via layer in the display area and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, light emitting elements on the first electrode and the second electrode spaced apart from each other on the first insulating layer, and a first connection electrode on the first electrode and electrically contacting the light emitting elements, and a second connection electrode on the second electrode and electrically contacting the light emitting elements, each of the conductive layers includes a first metal layer and a second metal layer on the first metal layer, and the second metal layer contains copper and has a grain size of about 155 nm or less.

A display device according to an embodiment includes a pixel and a bank. The pixel includes sub-pixels and an emission area including sub-emission areas corresponding to the sub-pixels. The bank surrounds the emission area. The pixel includes electrodes disposed in each of the sub-emission areas, at least one light emitting element disposed in each of the sub-emission areas, and bank patterns disposed under the electrodes, the bank patterns overlapping a portion of the electrodes. The bank patterns include a first bank pattern including a first valley, the first bank pattern being disposed in a first edge area of the emission area in a first direction. The bank patterns include a second bank pattern including a second valley, the second bank pattern being disposed in a second edge area of the emission area in the first direction.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

A semiconductor package includes: an insulating substrate having opposing first and second main sides; a power semiconductor die embedded in, and thinner than or a same thickness as, the substrate, and including a first load terminal bond pad at a first side which faces a same direction as the substrate first main side, a second load terminal bond pad at a second side which faces a same direction as the substrate second main side, and a control terminal bond pad; electrically conductive first vias extending through the substrate in a periphery region; a first metallization connecting the first load terminal bond pad to the first vias at the substrate first main side; solderable first contact pads at the substrate second main side and formed by the first vias; and a solderable second contact pad at the substrate second main side and formed by the second load terminal die bond pad.

A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

A display device may include a display area including pixel areas each including an emission area, a non-display area, and a pixel disposed in each of the pixel areas. The pixel may include a first electrode, a second electrode spaced apart from the first electrode and surrounding a periphery of the first electrode, a third electrode spaced apart from the second electrode and surrounding a periphery of the second electrode, a fourth electrode spaced apart from the third electrode and surrounding a periphery of the third electrode, light emitting elements disposed between the first to fourth electrodes, and first and second conductive lines disposed under the first to fourth electrodes with an insulating layer disposed therebetween. The first conductive line may be electrically connected to the first electrode, and the second conductive line may be electrically connected to the fourth electrode.

A display device may include a first scan line, a first data line and a second data line, a first read-out line and a second read-out line. A first sub-pixel may be connected to the first scan line, the first data line, and the first read-out line. A second sub-pixel may be connected to the first scan line, the first data line, and the second read-out line. A third sub-pixel may be connected to the first scan line, the second data line, and the first read-out line. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include at least one light emitting element.