A semiconductor device includes: a die pad having a top surface; a semiconductor chip provided on the top surface; a first solder provided between the top surface and the semiconductor chip, the first solder bonding the top surface and the semiconductor chip; a first metal film provided on the semiconductor chip; a first insulating film provided on the first metal film and having a first opening; a connector having a first end and a second end, the first end being provided on the first metal film in the first opening; a second metal film provided in the first opening, the second metal film having a plurality of second openings provided so as to surround a portion of the first metal film in contact with the first end, and the second metal film being provided between the first end of the connector and the portion of the first metal film; a plurality of second insulating films provided in direct contact with the first metal film in each of the second openings; and a second solder provided between the second metal film and the first end to bond the first end and the second metal film to each other.

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The first electronic component is between the second and the third electronic components. The first interconnection structures are between the first and the second electronic components. Each first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component, and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between the second and the third electronic components, and electrically connected to the second and the third electronic components. A height of each second interconnection structure is different from a height of each first interconnection structure.

A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

A method for manufacturing a display panel includes providing a backplate, forming bonding parts on backplate, forming an auxiliary layer on backplate, releasing light-emitting elements onto the auxiliary layer such that electrodes of the light-emitting elements are in contact with the first parts to form an intermediate backplate, arranging the intermediate backplate under first predetermined condition under which a fluidity of the first part is greater than that of the second part, and bonding the electrodes and the bonding parts to form an eutectic bonding layer, and arranging the intermediate backplate under second predetermined condition such that the first and second parts form solid-state first and second members. The backplate includes first and second regions. The bonding parts are located in the first regions. The auxiliary layer covers the backplate and the bonding parts. The auxiliary layer includes first and second parts respectively located in the first and second regions.

A method for light-emitting element transferring includes: providing multiple light-emitting elements, each light-emitting element includes a first light-emitting unit, a substrate, and a second light-emitting unit sequentially stacked, the first light-emitting unit includes a first epitaxial structure and a first electrode group stacked on a side of the substrate, the second light-emitting unit includes a second epitaxial structure and a second electrode group stacked on another side of the substrate, and the first light-emitting unit and the second light-emitting unit have different light-emitting colors; providing a display backplane, multiple grooves are defined on the display backplane, a first pad group and a second pad group are provided on side walls of each groove; and embedding the multiple light-emitting elements into the multiple grooves in one-to-one correspondence, where the first electrode group is bonded with the first pad group, and the second electrode group is bonded with the second pad group.

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.