In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

A molded semiconductor module include: a semiconductor die attached to a main surface of a metal block. The die has a metal contact pad at a side of the die facing away from the metal block. A metal terminal has a contact region attached to the metal contact pad of the die, and a distal end region that joins the contact region and is bent upward in a direction away from the metal block such that the distal end region has a free end which terminates at a further distance from the metal block than the contact region. A molding compound encapsulates the die and covers the contact region of the metal terminal. The distal end region of the metal terminal protrudes through a surface of the molding compound that faces a same direction as the side of the die with the metal contact pad.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a tack agent on the substrate, placing the die on the substrate, placing the clip on the die and the substrate to create a substrate, die and clip package, and sintering the substrate, die and clip package.

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

An electronic module has a sealing part 90; a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; a rear surface-unexposed conductor 40, 50 whose rear surface is not exposed; an electronic element 15, 25, which is provided in the sealing part 90 and provided on a front surface of the rear surface-exposed conductor 40, 50; a first connector 60 for electrically connecting the electronic element 15, 25 with the rear surface-exposed conductor 10, 20, 30; and a second connector 70 for electrically connecting the electronic element 15, 25 with the rear surface-unexposed conductor 40, 50. A thickness T1 of the first connector 60 is thicker than a thickness T2 of the second connector 70.

A semiconductor module includes: a board; a semiconductor device disposed on the board, a first surface of the semiconductor device closer to the board being connected to the board; an interconnection layer to which a second surface of the semiconductor device opposite to the first surface is connected, and which has a recess portion on an opposite surface to a surface closer to the semiconductor device; a first metal film disposed in the recess portion of the interconnection layer via a bonding film, and that is electrically connected to the interconnection layer; an insulating layer disposed on the first metal film; and a heat transfer plate disposed on the insulating layer.

A method of making a plurality of integrated circuit (“IC”) packages includes picking up a plurality of physically unconnected IC components; and simultaneously placing each of the physically unconnected IC components on corresponding portions of an unsingulated IC package strip that includes a sheet of integrally connected leadframes.

A semiconductor package includes a carrier having a recess, a semiconductor die arranged on the carrier such that a first side of the semiconductor die faces the carrier, and a contact clip arranged over a second side of the semiconductor die, opposite the first side. The contact clip includes a lowered part. The lowered part is arranged in the recess.