A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A circuit includes a conductive clip coupled to at least one component in the circuit. At least one lead portion is located on an end of the clip. The circuit further includes a first lead frame having at least one opening sized to receive the at least one lead portion. The at least one lead portion is received in the at least one opening and the at least one lead portion is an external conductor of the circuit.

An integrated circuit (IC) package, e.g., a power MOSFET package, may include a lead frame including (a) a main lead frame structure including a plurality of leads and defining or lying in a main lead frame plane, and (b) an offset lead frame die-attach pad (DAP) defining or lying in an offset plane that is offset from the main lead frame plane. The power IC package may further include a semiconductor die having a first side attached to the offset lead frame DAP, and a conductive element attached to both (a) a second side of the semiconductor die and (b) the main lead frame structure. The lead frame including the offset DAP may emulate the functionality of a copper clip, thus eliminating the need for the copper clip. The power IC package may also exhibit enhanced heat dissipation capabilities.

A semiconductor apparatus according to the present invention is a semiconductor apparatus on which a plurality of external terminals are disposed. The semiconductor apparatus includes: a first lead portions having die pads, first outer leads and first inner leads; chips; second lead portions having second outer leads and second inner lead; and a resin. On at least one of the first inner leads, the second inner leads and the die pads, a terminal temperature equalizing structure which restricts a heat transfer amount of heat transferred from the chips to predetermined external terminals, and equalizes respective terminal temperatures of a plurality of external terminals is formed. According to the semiconductor apparatus of the present invention, it is possible to prevent specific external terminals from becoming extremely high temperature when the semiconductor apparatus is mounted.

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar.

A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures. The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly. The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly. The method includes forming a conductive layer on the conductive flank surfaces. The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer.

A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures. The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly. The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly. The method includes forming a conductive layer on the conductive flank surfaces. The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer.

A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

A semiconductor package includes a metal baseplate, first and second HEMT dies each including a main surface with source, drain and gate terminals disposed thereon, a plurality of metal package terminals, and an encapsulant body of electrically insulating material, wherein the first and second HEMT dies are mounted on the metal baseplate with the main surfaces from each of the first and second HEMT dies facing away from the metal baseplate, wherein the encapsulant body encapsulates the first and second HEMT dies, wherein outer ends from each of the metal package terminals are exposed from the encapsulant body, and wherein each of the source, drain and gate terminals from the first and second HEMT dies is electrically connected via a bond wire-free connection to at least one of the metal package terminals.