A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

A semiconductor module is provided with a conductive member having one end, in a longitudinal direction, joined to an electrode of a semiconductor element that is mounted on an insulating substrate, the other end of the conductive member in the longitudinal direction being joined to a component different from the electrode. The conductive member is made up of a metal sheet, and has a bent portion at the one end and at the other end. The bent portion provided at the one end has a cut in a leading end portion, in the longitudinal direction, and an end joining section at which the cut is not present is joined to the electrode of the semiconductor element. As a result, a semiconductor module can be realized that allows combination of increased current capacity with improved reliability.

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

A power semiconductor package is disclosed. The power semiconductor package includes a leadframe having partially etched segments and at least one non-etched segment, a first semiconductor die having a first power transistor and a driver integrated circuit (IC) monolithically formed thereon, a second semiconductor die having a second power transistor, wherein the first semiconductor die and the second semiconductor die are configured for attachment to the partially etched segments, and wherein the partially etched segments and the at least one non-etched segment enable the first semiconductor die to be coupled to the second semiconductor die by a legless conductive clip.

A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

In one example, a method of manufacturing a semiconductor device includes providing a substrate having substrate terminals and providing a component having a first component terminal and a second component terminal adjacent to a first major side of the component. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first component terminal and a first substrate terminal and coupling the second clip to a second substrate terminal. The method includes encapsulating the component, portions of the substrate, and portions of the clip structure. the method includes removing a sacrificial portion of the clip connector while leaving a first portion of the clip connector attached to the first clip and leaving a second portion of the clip connector attached to the second clip. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant after the removing. Other examples and related structures are also disclosed herein.