Patent classifications
H01L24/41
FLIP-STACK TYPE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
Electronic module with a groove and press hole on the surface of a conductor
An electronic module has a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; an electronic element 15, 25 provided on a front surface of the rear surface-exposed conductor 10, 20, 30; and a connector 60 configure to connect the rear surface-exposed conductor 10, 20, 30 and the electronic element 15, 25 or two rear surface-exposed conductors 10, 20, 30 each other. A groove 150 is provided on the front surface of the rear surface-exposed conductor 10, 20, 30. The sealing part 90 is provided with a press hole or a press impression 110, 120, 130 used to press the rear surface-exposed conductor 10, 20, 30. In an in-plane direction, a center portion of the press hole or the press impression 110, 120, 130 is provided on the side opposite to the connector 60 or the electronic element 15, 25 with respect to the groove 150.
Electronic module with press hole to expose surface of a conductor
An electronic module has a sealing part 90; electronic elements 15, 25 provided in the sealing part 90; rear surface-exposed conductors 10, 20, 30 having rear surface-exposed parts whose rear surface are exposed from the sealing part 90, and having one-terminal parts 11, 21, 31, which extend from the rear surface-exposed parts 12, 22, 32 and protrude outwardly from a side of the sealing part 90; and rear surface-unexposed conductors 40, 50 having unexposed parts 42, 52, which are sealed in the sealing part 90, and having other-terminal parts 41, 51, which extend from the unexposed parts 42, 52 and protrude outwardly from a side of the sealing part 90. The electronic elements 15, 25 are placed on the rear surface-exposed parts 12, 22, 32. The other-terminal parts 41, 51 have a width narrower than a width of the one-terminal parts 11, 21, 31.
Stacked dies electrically connected to a package substrate by lead terminals
An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.
SEMICONDUCTOR MODULE
A semiconductor module includes a multilayer substrate having an insulating plate on which first to third conductive layers respectively connected to positive, negative and output electrode terminals are arranged in a first direction, a plurality of first semiconductor elements each having top and bottom electrodes on the first conductive layer and arranged in a second direction orthogonal to the first direction, a plurality of second semiconductor elements each having top and bottom electrodes on the second conductive layer and arranged in the second direction, first and second main wiring members each connecting the top electrode of each first and second semiconductor element to the second and third conductive layers. The multilayer substrate includes a first control wiring layer extending in the second direction and passing under the first main wiring member, and a second control wiring layer extending in the second direction and passing under the second main wiring member.
Semiconductor package with solder standoff
A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
Power semiconductor device package
In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.
Integrated Circuit Having Die Attach Materials with Channels and Process of Implementing the Same
A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
Chip packaging device, chip packaging method, and package chip
The present disclosure provides a chip packaging device, a chip packaging method, and a package chip, and is related to a technical field of chip packaging. The chip packaging device includes conductive sheets, a vacuum suction movable assembly defining a variable suction surface, and a heating assembly. The variable suction surface sucks the plurality of conductive sheets. A first end of each of the conductive sheets is disposed above a corresponding bonding pads. A second end of each of the conductive sheets is disposed above a corresponding welding pin, so that when the variable suction surface is pressed down, the first end of each of the conductive sheets is pressed onto the corresponding bonding pad, and the second end of each of the conductive sheets is pressed onto the corresponding welding pin. The heating assembly heats solders on the bonding pads and the welding pins.
Techniques for forming semiconductor device packages and related packages, intermediate products, and methods
Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.