A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.

In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.

A die is described comprising at least one 3-way Doherty amplifier comprising a main stage, a first peak stage and a second peak stage. An input is connected to an input network which is connected to the main stage, first peak stage and second peak stage. The input network includes a first impedance connected to an input of the first peak stage and providing a −90° phase shift and a second impedance connected to an input of the second peak stage and providing a 90° phase shift. An output is connected to an output network which is connected to the main stage, first peak stage and second peak stage. The output network includes a third impedance connected to the output of the first peak stage and providing a 180° phase shift and a fourth impedance connected to the output of the main stage and providing a 90° phase shift.

Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.

Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

An electronic component package includes a frame, an electronic component, an encapsulant, a metal layer, and a redistribution layer. The frame has a through hole. The electronic component is disposed in the through hole of the frame and has an active surface on which electrode pads are formed and an inactive surface opposing the active surface. The encapsulant covers the inactive surface of the electronic component and is disposed between the frame and the electronic component within the through hole. The metal layer is formed on a surface of the encapsulant. The redistribution layer is disposed adjacently to the active surface of the electronic component and electrically connected to the electrode pads.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Various embodiments provide for flexible and robust power grid connectivity in a server on a chip environment. The power grid has three parallel conductors, (e.g., wires) which represent two power polarities. The outside two wires can be of a first polarity (e.g. Vdd), while the middle wire is of a second polarity (e.g., Vss). The polarities of the wires can also be switched, as long as the two outside wires have the same polarity, while the inside wire has a different polarity. Power pins from modules adjacent to the set of three wires make connections to the nearest wire of the matching polarity. In this way, every power pin on the modules can be connected to the power grid without need for special alignment or custom power pins.

The present disclosure relates to branched proximal connectors for high density neural interfaces and methods of microfabricating the branched proximal connectors. Particularly, aspects of the present disclosure are directed to a branched connector that includes a main body having a base portion of a supporting structure and a plurality of conductive traces formed on the base portion, and a plurality of plugs extending from the main body. Each plug of the plurality of plugs include an end portion of the supporting structure comprised of the one or more layers of dielectric material, and a subset of conductive traces from the plurality of conductive traces. Each trace from the subset of conductive traces terminates at a bond pad exposed on a surface of the end portion of the supporting structure.

A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.