A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed.

A method of determining a bonding status between a wire and at least one bonding location of a workpiece is provided. The method includes the steps of: (a) bonding a portion of a wire to a bonding location of a workpiece using a bonding tool of a wire bonding machine; (b) determining a motion profile of the bonding tool for determining if the portion of the wire is bonded to the bonding location, the motion profile being configured to result in the wire being broken during the motion profile if the portion of the wire is not bonded to the bonding location; and (c) moving the bonding tool along the motion profile to determine if the portion of the wire is bonded to the bonding location. Other methods of determining a bonding status between a wire and at least one bonding location of a workpiece are also provided.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.

A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic/processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function/model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.

An object is to provide a technique capable of suppressing generation of a crack in a molding resin and suppressing entry of moisture from the outside. A semiconductor device includes a heat spreader, a semiconductor element provided on an upper surface of the heat spreader, an insulating sheet provided on a lower surface of the heat spreader, a lead frame joined to an upper surface of the semiconductor element via solder, and a molding resin that seals one end side of the lead frame, the semiconductor element, the heat spreader, and the insulating sheet. A hole is formed from an upper surface of the molding resin to a joining surface of the lead frame with the semiconductor element, and the hole is filled with a low Young's modulus resin having a Young's modulus lower than that of the molding resin.

A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.