Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.

A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. A filter circuit can be integrally formed between the first and second elements along the bonding interface.

Examples are disclosed that relate to flexible electrical interconnects in electronic devices. One example provides a device including a flexible substrate, a conductive trace disposed on the flexible substrate, an electronic component mounted to the flexible substrate, a liquid metal interconnect bridging between a pad on the component and the trace on the flexible substrate, and an encapsulant covering the interconnect.

LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.

An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

The cap (1) is intended to be assembled with at least one chipped element (2), said cap comprising a stack of a plurality of electrically insulating layers (1a) delimiting at least one shoulder (3) forming a part of a first groove (4) for housing a wired element (12). The cap further comprises: at least one electrical bump contact (6) arranged at an assembly surface (7) of the stack intended to be mounted on a face of the chipped element (2); at least one electrical connection terminal (5, 5) arranged at a wall of the shoulder (3); an electrical link element (8), electrically linking said electrical connection terminal (5) to the electrical bump contact (6).

An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.

A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.