Patent classifications
H01L25/042
OPTOELECTRONIC SEMICONDUCTOR COMPONENT
A method of producing an optoelectronic semiconductor component includes providing a carrier; arranging at least one optoelectronic semiconductor chip at a top side of the carrier, wherein the semiconductor chip includes semiconductor layers deposited on a substrate; forming a shaped body around the at least one optoelectronic semiconductor chip, wherein the shaped body surrounds all side areas of the at least one optoelectronic semiconductor chip and at least some of the layers deposited on the substrate are free of the shaped body such that these layers are not covered or completely exposed; and removing the carrier.
Linear image sensor and method for manufacturing same
A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.
Semiconductor package and manufacturing method thereof
A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.
Visually undistorted thin film electronic devices
Visually undistorted thin film electronic devices are provided. In one embodiment, a method for producing a thin-film electronic device comprises: opening a scribe in a stack of thin film material layers deposited on a substrate to define an active region and an inactive region of the thin-film electronic device, the stack comprising at least one active semiconductor layer. The active region comprises a non-scribed area of the stack and the inactive region comprises a region of the stack where thin film material was removed by the scribe. The method further comprises depositing at least one scribe fill material into a gap opened by the scribe. The scribe fill material has embedded therein one or more coloring elements that alter an optical characteristics spectrum of the inactive region to obtain an optical characteristics spectrum of the active region within a minimum perceptible difference for an industry defined standard observer.
Radio-frequency module having RF and front-end integrated circuits
A radio-frequency module includes a radio-frequency integrated circuit (RFIC) including a base connection terminal, and a first radio-frequency (RF) connection terminal; a first connection member including a mounting area on which the RFIC is mounted, a base wiring electrically connected to the base connection terminal of the RFIC, and a first RF wiring electrically connected to the first RF connection terminal of the RFIC; a second connection member including a second RF wiring electrically connected to the first RF wiring of the first connection member, and a third RF wiring, at least a portion of the second connection member being more flexible than the first connection member; and a front-end integrated circuit (FEIC) mounted on the second connection member and configured to amplify the first RF signal to generate the first communications signal or amplify the first communications signal to generate the first RF signal.
ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF
An electronic device and a fabrication method thereof are provided. The electronic device includes a circuit structure layer, a package structure, an electronic element, and a plurality of function elements. The circuit structure layer has a first side and a second side opposite to the first side. The package structure is disposed on the first side of the circuit structure layer. The electronic element is embedded or encapsulated in the package structure. The function elements are disposed on the second side of the circuit structure layer. The function elements are electrically connected to the electronic element through the circuit structure layer. The electronic device provided by the disclosure exhibits borderless design or has a large function region.
Superlattice photo detector
A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.
Semiconductor arrangement, laminated semiconductor arrangement and method for fabricating a semiconductor arrangement
A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
Radiation imaging apparatus, manufacturing method thereof, and radiation imaging system
A radiation imaging apparatus includes a sensor base, a sensor array that includes a plurality of sensor chips arranged in an array, and in which three or more sensor chips out of the plurality of sensor chips are arranged in one row of the sensor array, a scintillator positioned on a side opposite to the sensor base with respect to the sensor array, a bonding member that bonds the sensor array and the scintillator, and a plurality of bonding sheets that are separated from each other and bond the sensor base and the plurality of sensor chips. Two adjacent sensor chips out of the three or more sensor chips are bonded to the sensor base using separate bonding sheets out of the plurality of bonding sheets.
Bonded nanofluidic device chip stacks
A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.