The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array. An integrated structure according to the present disclosure includes a first substrate including a plurality of photodiodes, an interconnect structure disposed on the first substrate, a first bonding layer disposed on the interconnect structure, a second bonding layer disposed on the first bonding layer, a second substrate disposed on the second bonding layer, and a transparent conductive oxide layer disposed on the second substrate.

A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

There is provided a light trapping dynamic photovoltaic module having a module surface configured to be exposed to solar rays, including a plurality of photovoltaic cell stacks configured adjacent to each other throughout the module surface, wherein each photovoltaic cell stack comprises a plurality of photovoltaic cells. Further, a plurality of reflective strips are placed in between each of the photovoltaic cell stacks for continuously reflecting incident solar rays from one reflective strip to another until absorbed by a photovoltaic cell among said plurality of photovoltaic cells, wherein the incident solar rays are continuously reflected through a mirror phenomenon, wherein the incident solar rays are additionally reflected by front and back panels of the dynamic photovoltaic module, thereby trapping incident solar rays within boundaries of the dynamic photovoltaic module for conversion into electrical energy. Also disclosed is a method of manufacturing the light trapping photovoltaic module.

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

A photovoltaic module employing an array of photovoltaic cells disposed between two optically transparent substrates such as to define a closed-loop peripheral area of the module that does not contain a photovoltaic cell. The module is sealed with a peripheral seal along the perimeter; and is devoid of a structural element affixed to an optically transparent substrate and adapted to mount the module to a supporting structure. The two substrates may be bonded together with adhesive material and, optionally, the peripheral seal can include the adhesive material. The module optionally includes diffraction grating element(s) adjoining respectively corresponding PV-cell(s).

A solar panel includes a silicon cells submodule of silicon based cells, a front transparent plate and a backsheet. The backsheet is arranged with at least a first conductive pattern that is connected to rear surface electrical contacts on each of the silicon cells. A thin film photovoltaic submodule is arranged between the front transparent plate and the silicon cells, and includes thin film cells in an arrangement with two photovoltaic submodule contacts that connect to a second conductive pattern on the backsheet. The backsheet is arranged for four-terminal wiring with the first pattern for the silicon cells and the second pattern for the thin film cells. The thin film cells are disposed in a first group of cells and in at least a second group of cells, each connected in series. The first group is connected in parallel with the second group, between the photovoltaic submodule contacts.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.

Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

A photonic device manufacturing method, including a step of transfer, onto a same surface of a photonic circuit previously formed inside and on top of a first substrate, of at least a first die made up of a III-V semiconductor material and of at least a second die made up of silicon nitride, the method further including a step of forming of photonic components in said at least one first and at least one second dies.