Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A photovoltaic device includes a first group of photovoltaic cells of a first cell type, the first group of photovoltaic cells operable to produce a first current and a first voltage, and a second group of photovoltaic cells of a second cell type that is different than the first cell type, the second group of photovoltaic cells operable to produce a second current and a second voltage. A first power electronics unit is connected to the first group of photovoltaic cells, and a second power electronics unit is connected to the second group of photovoltaic cells. The second power electronics unit is separate from and not communicating with the first power electronics unit. A control device is operable to vary a first property of the first power electronics unit to vary the first current and the first voltage and to vary a second property of the second power electronics unit to vary the second voltage and the second current independent of the first voltage and the first current.

A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad. The second diode is in the semiconductor wafer, and is coupled to the first diode and the TO pad. The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer. The first signal tap region is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.