An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

A foldable doll includes: a doll body which is a hollow structure; a projection lamp disposed in the doll body; a power connector electrically connected to the projection lamp; a supporting assembly for supporting the doll body; a plurality of supporting rings sewn on the doll body; a blower connected to the doll body and electrically connected to the power connector. The projection lamp includes a lamp cover, a motor, and a projection unit. The motor includes a rotation shaft, and the projection unit is fixedly disposed on the rotation shaft and configured to emit and project light on the lamp cover. The blower is electrically connected to the power connector. In an unfolded state, the doll body is propped up by the supporting assembly, and in a folded state, the supporting assembly is detached from the doll body, and the doll body automatically collapses by gravity.

A semiconductor apparatus and a fabrication method thereof are disclosed. The semiconductor apparatus includes a substrate, a channel layer, a barrier layer, and a gate structure, and includes: a first doped group III-V semiconductor, a group III-V semiconductor, and a conductor. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the doped group III-V semiconductor. The conductor is disposed on the group III-V semiconductor, where a width of the first doped group III-V semiconductor is greater than a width of the conductor.

A semiconductor device includes a semiconductor element, an electronic component electrically connected to the semiconductor element, a connection member electrically connecting the electronic component to the semiconductor element, and a sealing resin portion having a first surface and a second surface opposite to the first surface and integrally holding the semiconductor element, the electronic component, and the connection member in a state where a semiconductor top surface as a surface of the semiconductor element and a component surface as a surface of the electronic component are exposed from the sealing resin portion on a side adjacent to the first surface.

In accordance with one or more embodiments herein, a method of manufacturing a photovoltaic (PV) top module, to be used together with a PV bottom module, e.g an SI-based PV bottom module, is provided. The method may include monolithically interconnecting a plurality of thin film based PV sub-cells, manufactured using a perovskite material and/or a CIGS material as solar absorbing material, in series on a substrate in order to create a PV top module including at least one first PV top sub-module, and arranging metal grid lines on top and bottom contact layers of the PV top module. The metal grid lines may be arranged either above or below the top and bottom contact layers of the PV top module.

A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

A photoelectric conversion apparatus includes a first and a second multilayer wiring layer. The first or the second multilayer wiring layer is provided with a first electrode supplied with a first voltage from an outside of the photoelectric conversion apparatus. The first electrode is not connected with a second semiconductor layer.

Embodiments of the disclosure provide an optical sensing system and an optical sensing method thereof. The optical sensing system comprises a light source configured to emit an optical signal into an environment surrounding the optical sensing system. The optical sensing system further comprises a photodetector configured to receive the optical signal reflected from the environment of the optical sensing system, and convert the optical signal to an electrical signal, where the photodetector is disposed in a package. The optical sensing system additionally comprises a readout circuit configured to generate a readout signal based on the electrical signal received from the photodetector, where the readout circuit is disposed in the same package as the photodetector and connected to the photodetector through routings in the package.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A solar panel includes a silicon cells submodule of silicon based cells, a front transparent plate and a backsheet. The backsheet is arranged with at least a first conductive pattern that is connected to rear surface electrical contacts on each of the silicon cells. A thin film photovoltaic submodule is arranged between the front transparent plate and the silicon cells, and includes thin film cells in an arrangement with two photovoltaic submodule contacts that connect to a second conductive pattern on the backsheet. The backsheet is arranged for four-terminal wiring with the first pattern for the silicon cells and the second pattern for the thin film cells. The thin film cells are disposed in a first group of cells and in at least a second group of cells, each connected in series. The first group is connected in parallel with the second group, between the photovoltaic submodule contacts.