A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.

An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

A semiconductor memory device according to an embodiment includes a substrate, a first conductor layer, second conductor layers, a first semiconductor layer, a pillar, and a contact. The pillar has a portion provided to penetrate the second conductor layers and the first semiconductor layer. The contact is electrically connected to the pillar and the first conductor layer. The pillar includes a second semiconductor layer, a first insulator layer provided at least between the second semiconductor layer and the second conductor layers, and a third semiconductor layer provided between the second semiconductor layer and the first semiconductor layer and in contact with each of the second semiconductor layer and the first semiconductor layer.

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.