An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

A semiconductor device having a substrate, a semiconductor chip, and a plurality of electrode terminals is provided. The substrate has first and second principal surfaces. The semiconductor chip is disposed on the first principal surface. The electrode terminals are disposed on the second principal surface. The substrate has a via interconnection near a position at which an outer edge line of the semiconductor chip intersects an outer outline of the electrode terminal farthest from a center of the substrate, the electrode terminal farthest from the center of the substrate being among the plurality of electrode terminals overlapping the outer edge line in a predetermined condition as seen through the substrate of the semiconductor device from a direction perpendicular to the first principal surface, the via interconnection connecting a first interconnection layer on a first principal surface-side to a second interconnection layer on a second principal surface-side.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

A stack package includes a package substrate; a lower stack including lower dies stacked on the package substrate to form a zigzag shape in a vertical direction; an upper stack including upper dies that are sequentially offset stacked in an offset direction while providing a first upper side of a down staircase shape, a first end of an uppermost upper die among the upper dies protruding, in a horizontal direction, further than a first lower side of the lower stack; and a first passive device disposed on the package substrate and spaced apart from the first lower side, and disposed between a first portion of the package substrate and the first upper side.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure. The protruding end portion of each of the plurality of channel structures extends into the source layer. The protruding end portion of each of the plurality of channel structures has a flat section.

A semiconductor device includes a first memory array which includes a first memory string including a plurality of first memory cells arranged in a vertical direction. The first memory array further includes a first conductive structure operatively coupled to the first memory string that extends through the first memory array in the vertical direction. The semiconductor device further includes a second memory array including a second memory string including a plurality of second memory cells arranged in the vertical direction. The second memory array further includes a second conductive structure operatively coupled to the second memory string that extends through the second memory array in the vertical direction. The semiconductor device further includes a bowl-shaped conductive structure interposed between the first and second memory arrays, and configured to operatively couple the first conductive structure to the second conductive structure.