Provided is a technique for reducing the size and cost of a semiconductor device. A semiconductor device includes an IGBT module having an IGBT, and a MOSFET module having a MOSFET whose operational property is different from that of the IGBT, the MOSFET module being connected to the IGBT module in parallel. The semiconductor device is capable of selectively executing an operation mode in which switching timing in the IGBT module and switching timing in the MOSFET module are non-identical.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

An apparatus includes a busbar and a heat-generating electronic device mounted on a first side of the busbar, the heat-generating electronic device being electrically and thermally coupled to the first side of the busbar. The busbar includes an array of non-planar physical structures on a second side of the busbar opposite the first side of the busbar. The apparatus includes a dielectric coating on the array of non-planar physical structures, the dielectric coating defining a non-planar dielectric surface on the second side of the busbar.

Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.

A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.

An electronic module has a first substrate 11; a first electronic element 13 provided on one side of the first substrate 11; a first connection body 60 provided on the one side of the first electronic element 13; a second electronic element 23 provided on the one side of the first connection body 60; and a second connection body 70 provided on the one side of the second electronic element 23. The first electronic element 13 and the second electronic element 23 do not overlap in a plane direction.

A performance of a semiconductor device including a main MOSFET and a sensing MOSFET having a double-gate structure including a gate electrode and a field plate electrode inside a trench is improved. A main MOSFET including a gate electrode and a field plate electrode inside a second trench and a sensing MOSFET for electric-current detection including a gate electrode and a field plate electrode inside a fourth trench are surrounded by different termination rings, respectively.

A semiconductor device includes a substrate, a first chip, a second chip, a first connector, and a second connector. The substrate has a second thickness. The first chip includes a first surface facing the substrate, a second surface positioned at a side opposite to the first surface, a first electrode located at the first surface and electrically connected to the substrate, and a second electrode located at the second surface. The second connector includes a first part positioned above the second chip. A difference between the second thickness and a first thickness of the first part is not more than 20% of the greater of the first thickness or the second thickness.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.