A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.

A semiconductor module includes: two semiconductor elements stacked in a vertical direction to overlap at least a part of the semiconductor elements; a conductive member stacked on the semiconductor elements and electrically connected to at least one of the semiconductor elements; and a resin mold integrally sealing the semiconductor elements and the conductive member. A lower semiconductor element has at least observable positions of both ends of two sides substantially orthogonal to each other when viewed from above in the vertical direction without arranging the resin mold.

Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion, with the O lead frame located between the N lead frame and the P lead frame. The power card includes a first power device being located on a first side of the O lead frame and a second power device being located on a second side of the O lead frame, the body portion of the O lead frame having one or more channels configured to receive a cooling liquid for cooling the first power device and the second power device.

A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

A semiconductor device includes semiconductor elements, an insulating member, first and second terminals and control terminals. The semiconductor elements each include a semiconductor part, a first electrode on the back surface of the semiconductor part, a second electrode and a control electrode on the front surface thereof. The semiconductor elements are electrically connected in series and include first-end and second-end semiconductor elements each provided at an end of the series connection. The insulating member seals the semiconductor elements and includes a first surface and a second surface opposite to the first surface. The first and second terminals are electrically connected to the first electrode of the first-end semiconductor element and the second electrode of the second-end semiconductor element, respectively. Each control terminal is electrically connected to the control electrode. The second and control terminals are provided at one of the first or second surface side of the insulating member.

A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

A light emitting diode (LED) pixel for a display including a light emitting structure configured to generate light and comprising at least one active layer, a first passivation layer surrounding side surfaces and an upper portion of the light emitting structure, the first passivation layer including via holes, and a plurality of via contacts filling the via holes and electrically connected to the light emitting structure, in which the via holes do not overlap the at least one active layer, and an area of the first passivation layer is greater than that of the light emitting structure in plan view.

An electronic module has a first substrate 11, a first conductor layer 12 that is provided on one side of the first substrate 11, a first electronic element 13 that is provided on one side of the first conductor layer 12, a second electronic element 23 that is provided on one side of the first electronic element 23, and a second connecting body 70 that has a second head part 71 provided on one side of the second electronic element 23 and an extending part 75 extending from the second head part 71 to the other side and abutting against the first substrate 11 or the first conductor layer 12.