A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.

Various embodiments include a power module comprising: a first power electronics device arranged on a first substrate board; and a second power electronics device mounted on a second substrate board. The first substrate board, the first device, the second substrate board, and the second device are arranged on a first baseplate stacked above one another or in planar fashion beside one another.

A foldable doll includes: a doll body which is a hollow structure; a projection lamp disposed in the doll body; a power connector electrically connected to the projection lamp; a supporting assembly for supporting the doll body; a plurality of supporting rings sewn on the doll body; a blower connected to the doll body and electrically connected to the power connector. The projection lamp includes a lamp cover, a motor, and a projection unit. The motor includes a rotation shaft, and the projection unit is fixedly disposed on the rotation shaft and configured to emit and project light on the lamp cover. The blower is electrically connected to the power connector. In an unfolded state, the doll body is propped up by the supporting assembly, and in a folded state, the supporting assembly is detached from the doll body, and the doll body automatically collapses by gravity.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A diode pack housing for a rotating rectifier assembly can include a body having an interior surface defining an interior cavity open on a first end and configured to contain a diode pack and a plurality of bus bar channels defined axially on or in the inner surface in the interior cavity. The plurality of bus bar channels can be five or less bus bar channels.

A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.

A semiconductor device includes a substrate, a first FET part and a second FET part disposed on a surface of the substrate. The first FET part includes a first gate electrode region and a first source electrode region spaced apart from each other. The second FET part, connected to the first FET part in a stacked structure, includes a second gate electrode region and a second drain electrode region spaced apart from each other. Each of the first FET part and the second FET part includes a first common electrode and a second common electrode disposed on the surface of the substrate and spaced apart from each other. Each of the first common electrode and the second common electrode is configured to be a single conductor wiring integrally formed by a first drain electrode of the first FET part and a second source electrode of the second FET part.

A semiconductor device includes a semiconductor element, a conductive member and a connecting member. The semiconductor element has a reverse surface formed with a first electrode and an obverse surface formed with a second electrode and a third electrode. The reverse surface and the obverse surface are spaced apart from each other in a z direction. Current flow between the first electrode and the second electrode is on-off controlled according to a first drive signal inputted to the third electrode. The conductive member has a first bond surface and a second bond surface each facing in the same direction as the reverse surface. The third electrode is bonded to the first bond surface. The connecting member is bonded to the second bond surface, and the second bond surface does not overlap with the semiconductor element as viewed in the z direction.

A semiconductor device includes a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed on a first front surface of the first semiconductor chip, and a first drain electrode is formed on a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed on a second front surface of the second semiconductor chip, and a second drain electrode is formed on a second back surface of the second semiconductor chip. The first back surface and the second back surface are faced to each other such that the first drain electrode and the second drain electrode are in contact with each other via a conductive tape.