A display module includes a substrate including a mounting surface and a side surface; a Thin Film Transistor (TFT) layer provided on the mounting surface of the substrate; a plurality of inorganic light emitting diodes mounted on the mounting surface of the substrate; an anisotropic conductive layer provided on an upper surface of the TFT layer and electrically connecting the TFT layer to the plurality of inorganic light emitting diodes; a front cover covering the mounting surface; and a side cover surrounding the side surface. A side end of the front cover extends to a region outside the mounting surface, the side cover is bonded to a lower surface of the front cover and to the side surface of the substrate which correspond to the region outside of the mounting surface, and a side end of the anisotropic conductive layer is provided on an inner side with respect to the side end of the front cover.

The present invention provides an array substrate and a display panel. The array substrate includes: an underlay; a source electrode and drain electrode disposed on underlay; a light shielding portion disposed on underlay; an active layer correspondingly disposed on the source electrode, the drain electrode, and the light shielding portion. The active layer includes a channel region, and the light shielding portion is disposed to correspond to the channel region. The present invention reduces processes and lowers cost by disposing the source electrode, the drain electrode, and the light shielding portion in a same layer such that the source electrode, the drain electrode, and the light shielding portion are simultaneously formed with a same material by a same process.

A display is provided. The display includes a first substrate comprising a plurality of electrode pads disposed on a front surface, a plurality of solder members disposed on a rear surface, and a plurality of wiring members electrically connecting the plurality of electrode pads and the plurality of solder members, respectively, a plurality of light-emitting elements electrically connected to each of the plurality of electrode pads, and constituting pixels of two columns, and a second substrate comprising a thin film transistor (TFT) layer disposed on a rear side of the first substrate and electrically connected to the plurality of solder members to control driving of the plurality of light-emitting elements, and the first substrate may include a first region in which pixels of a first column are disposed, a second region in which pixels of a second column are disposed, and a third region disposed between the first region and the second region, the plurality of wiring members may be disposed on the first region and the second region among the front surface of the first substrate.

A display device is provided. The display device comprising: a substrate including a display area and a pad area, a first conductive layer disposed on the substrate and including a first signal line disposed in the display area, a buffer layer disposed on the first conductive layer, a semiconductor layer disposed on the buffer layer in the display area, a gate insulating film disposed on the semiconductor layer, a second conductive layer disposed on the gate insulating film and including a gate electrode overlapping the semiconductor layer in the display area, a first electrode of a transistor disposed to overlap one side of the semiconductor layer in the display area and connected to the first signal line through a contact hole penetrating through the buffer layer and the gate insulating film, and a second electrode of the transistor disposed to overlap the other side of the semiconductor layer in the display area, a first pad disposed on the buffer layer in the pad area and exposed by a pad opening, a first insulating layer disposed on the second conductive layer and the first pad, and a light emitting element disposed on the first insulating layer in the display area, wherein the first pad is formed of the first conductive layer or the second conductive layer.

A semiconductor device is provided, which includes a substrate, a first semiconductor structure, a plurality of first holes, a first dielectric structure and a second semiconductor structure. The first semiconductor structure is located on the substrate. The first holes are periodically arranged in the first semiconductor structure. The first dielectric structure is filled in one or more of the first holes. The second semiconductor structure is located on the first semiconductor structure.

A light emitting assembly comprising at least one of each of a solid state device and a thermal radiation source, couplable with a power supply constructed and arranged to power the solid state device and the thermal radiation source, to emit from the solid state device a first, relatively shorter wavelength radiation, and to emit from the thermal radiation source non-visible infrared radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and the infrared radiation, and which in exposure to said first, relatively shorter wavelength radiation, and infrared radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue light output from a light-emitting diode is down-converted to white light by packaging the diode and the thermal radiation device with fluorescent or phosphorescent organic and/or inorganic fluorescers and phosphors in an enclosure.

A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

A display device includes a first planarization film including an opening, a reflective film provided on an inclined surface inside the opening in the first planarization film, an LED chip surrounded by the reflective film and provided inside the opening, and a second planarization film provided on the first planarization film, surrounding the LED chip, and filling the opening, wherein a height from an upper end of the inclined surface of the first planarization film to an interface with air in the second planarization film is 20 μm or less.

A display device includes pixels, each of the pixels including light emitting elements disposed in pixels, a color conversion layer disposed on the light emitting elements of the pixels, an optical layer disposed on the color conversion layer, and an organic layer disposed on the optical layer. At least one of the optical layer and the organic layer includes recess patterns disposed between the pixels.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence including a first semiconductor layer, a second semiconductor layer, and an active layer arranged between the first semiconductor layer and the second semiconductor layer, a via having a plurality of recesses and a contact layer, wherein the first semiconductor layer has a first electrical contact region, wherein the second semiconductor layer has a second electrical contact region, wherein the via completely penetrates the first semiconductor layer and the active layer and is electrically connected to the second contact region, wherein the first contact region is arranged within the recesses of the via, and wherein the first contact region is divided into a plurality of partial regions, each partial region being arranged in one of the recesses and the partial regions being separated from each other.