Patent classifications
H01L25/115
PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.
Mounting devices for semiconductor packages with a fixation mechanism
The present disclosure concerns a mounting device for semiconductor packages, and a heat dissipation assembly with such a mounting device. The mounting device includes a bottom side comprising one or more cavities to house semiconductor packages, and a top side comprising a plurality of holes extending from the bottom side to the top side for accommodating contact pins of the semiconductor packages. A fixation mechanism fixes the mounting device to a heat dissipation structure.
POWER CONVERSION DEVICE
A power conversion device includes: semiconductor switching elements; a housing on which the semiconductor switching elements are fixed; a circuit board on which a driving circuit for driving the semiconductor switching elements is mounted and which is located opposite to and spaced apart from a fixing surface; insertion guides which are disposed on an opposing surface of the circuit board relative to the fixing surface; and elongated terminal extension members each having a length that is matched with a height of a pulse transformer, one ends of which are bonded to respective lead terminals, and the other ends of which extend toward the insertion guides; wherein the pulse transformer is disposed on the opposing surface so as to be opposite to major surfaces of the semiconductor switching elements.
Inverter
A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.
Three-dimensional packaging techniques for power FET density improvement
A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand “on end” so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.
Wafer level chip scale packaging intermediate structure apparatus and method
Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
SYSTEM FOR DRIVING POWER DEVICES
A system for driving power devices is provided, and the system includes a heat dissipation plate, semiconductor modules, gate plates, a control board, a bridge module, and a terminal module. The semiconductor modules are disposed on the heat dissipation plate. Each gate plate is disposed on the corresponding semiconductor module and includes first driving terminal. The control board is disposed on the heat dissipation plate. The bridge module and the terminal module are electrically connected to each other, disposed on the control board, and arranged sequentially in a direction from a center to an edge of the control board. The bridge module includes a plurality of driving bridge plates, and each driving bridge plate is electrically coupled to the control board. The terminal module includes a plurality of second driving terminals, and each second driving terminal is electrically connected to the corresponding driving bridge plate and first driving terminal.
SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR WITH BACK SIDE POWER STRUCTURE
A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.
SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor element; a sealing resin; a gate terminal; a drain terminal; a source terminal; a heat dissipation plate electrically connected to the drain, and protruding from a second side intersecting with a first side of the sealing resin in top view; and a heat dissipation plate electrically connected to the drain, and protruding from a third side opposing the second side of the sealing resin in top view. At least a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate or a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate are the same.
Power Component And System With The Power Component
A power component includes two electric terminals, a component housing, a main component at least partially surrounded by the component housing, connected with the two terminals, and configured to carry a power current flowing between the two electric terminals, and a sensor and emitter unit which is configured to measure a value of a physical quantity (T, V, ΔV) characterizing an operating state of the main component, and to emit an electromagnetic signal, in which the measured value of the physical quantity is encoded. The sensor and emitter unit includes an antenna for emitting the electromagnetic signal which is spaced apart from the main component and arranged in, on and/or at the component housing.