A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler.

An electronic component module includes an electronic component, a resin structure, a wiring portion, and a shield portion. The resin structure covers a second main surface and at least a portion of a side surface of the electronic component. The wiring portion is electrically connected to the electronic component. The shield portion includes a first conductor layer and a second conductor layer. The first conductor layer is spaced away from the electronic component between the electronic component and the resin structure, and has electrical conductivity. The second conductor layer is spaced away from the wiring portion between the wiring portion and the resin structure, and has electrical conductivity. In the shield portion, the first conductor layer and the second conductor layer are integrated.

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.

A light source device including a substrate, a plurality of first light emitting diode (LED) chips, and at least one second LED chip is provided. The substrate has an upper surface. The plurality of first LED chips are disposed on the upper surface and electrically connected to the substrate. Each of the first LED chips includes a first chip substrate, a first semiconductor layer, and a plurality of first electrodes, and the first electrodes are disposed on the upper surface of the substrate. The second LED chip is disposed on the upper surface and electrically connected to the substrate. The second LED chip includes a second chip substrate, a second semiconductor layer, and a plurality of second electrodes. A thickness of the second chip substrate is different from than a thickness of the first chip substrate, and the second electrodes are disposed on the upper surface of the substrate.

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.

A wiring substrate includes a core substrate and a cavity extending through the core substrate. The cavity has a planar shape that is rectangular, and includes corners and sides connecting the corners in a plan view. The wiring substrate also includes first through holes that extend through the core substrate and are spaced apart from the cavity. An electronic component is arranged in the cavity. The wiring substrate also includes a first insulating material with which the first through holes are filled and a second insulating material with which a gap between the electronic component and walls of the cavity is filled. The first through holes are arranged around the corners of the cavity in a plan view. Each of the first through holes is L-shaped in a plan view and formed continuously along two of the sides of the cavity that define the corresponding corner.