An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.

A display device includes: a substrate including a display area including a first pixel area, a component area adjacent to the display area, and a non-display area adjacent to the display area, where the component area includes a second pixel area and a transmission area, and the non-display area includes a bending area; a first inorganic layer continuously arranged in the transmission area on the substrate, where a lower opening overlapping the bending area is defined through the first inorganic layer; a blocking layer on the first inorganic layer, a blocking layer opening overlapping the transmission area and an intermediate opening overlapping the lower opening are defined through the blocking layer; and a display element layer on the blocking layer, where the display element layer includes a first display element overlapping the first pixel area and a second display element overlapping the second pixel area.

A display device including: a display area including a plurality of pixels; and a peripheral area disposed around the display area to include a driving signal transmission line, each of the pixels may include a transistor, a driving voltage line connected to the transistor and the driving signal transmission line, and a light emitting unit connected to the transistor, the pixels may include a first pixel and a second pixel spaced apart from the driving signal transmission line to have different distances from each other, and a concentration of impurities doped in a semiconductor layer of the transistor of the first pixel may be different from a concentration of impurities doped in a semiconductor layer of the transistor of the second pixel.

The present disclosure is directed to display circuitry that can be formed on a flexible substrate. The circuitry includes a voltage divider formed from a first and second non-linear resistor device or a first and second transistor coupled in a diode configuration. The circuitry includes a driving thin film transistor coupled to the voltage divider. The non-linear resistor devices may include a lower electrode that is amorphous metal or a crystalline metal. The first and second transistor coupled in a diode configuration may have a lower electrode that is amorphous metal. Upper electrodes may be crystalline metal. The driving thin film transistors may have the lower electrode as amorphous or crystalline metal.

A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.

A display apparatus includes substrate a semiconductor layer on the substrate, and having a semiconductor pattern, a first conductive layer on the semiconductor layer, and including a first wiring that extends in a first direction, a second wiring that protrudes from the first wiring in a second direction crossing the first direction, and a driving gate electrode, and a second conductive layer on the first conductive layer, and including a first electrode that overlaps the driving gate electrode, wherein the semiconductor pattern includes a first pattern that extends in the first direction and overlaps the second wiring, and a second pattern that extends in the second direction and overlaps the first wiring, and wherein the first electrode includes a protruding electrode that overlaps at least part of the first pattern and at least part of the second pattern.

A display device includes a first data line configured to receive a first data voltage, a second data line configured to receive a second data voltage, a low driving voltage line configured to receive a low driving voltage, and a first sub-pixel connected to the first data line, the second data line, and the low driving voltage line. The first sub-pixel includes a cathode pad electrode connected to the low driving voltage line, a first transistor configured to generate a control current according to the first data voltage of the first data line and having a first gate electrode, an eighth transistor configured to generate a driving current applied to a light emitting element according to the second data voltage of the second data line, and a first capacitor including a first capacitor electrode connected to the first gate electrode, and a second capacitor electrode on the first capacitor electrode.

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

A display apparatus includes a plurality of pixels. A pixel includes a first capacitor connected between a first voltage line receiving a first driving signal and a first node, a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal and a second electrode connected to a second node, an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, a second capacitor connected between an m-th data line and the second node (wherein, ‘m’ is a natural number) and a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to the first node and a second electrode connected to the second node.

An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.