The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.

A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

According to one embodiment, a display device includes a first substrate, a second substrate, a liquid crystal layer including polymers and liquid crystal molecules, and a light-emitting element. The first substrate includes a transparent substrate, a scanning line, a signal line crossing the scanning line, a switching element electrically connected to the scanning line and the signal line, an organic insulating film overlapping the switching element, and a pixel electrode electrically connected to the switching element. A thickness of the organic insulating film located between the transparent substrate and the pixel electrode is less than a thickness of the organic insulating film overlapping the switching element.

A display device includes a first semiconductor pattern on a substrate, a first insulating layer on the first semiconductor pattern, a first gate electrode on the first insulating layer, a second insulating layer on the first gate electrode, a second semiconductor pattern on the second insulating layer, a material of the second semiconductor pattern being different from that of the first semiconductor pattern, a third insulating layer on the second semiconductor pattern, a second gate electrode on the third insulating layer, a first planarization layer overlapping the second gate electrode, a second planarization layer on the first planarization layer and including a light blocking portion, and a pixel definition layer on the second planarization layer, wherein at least a portion of the pixel definition layer directly contacts the light blocking portion of the second planarization layer.

An organic light-emitting display apparatus includes an organic light-emitting diode, a switching transistor, a first light emission control transistor, and a driving transistor. The organic light-emitting diode includes an anode and a cathode for receiving a reference voltage. The switching transistor includes a gate electrode for receiving an nth scan signal and a source electrode for receiving a data signal, and is an NMOS transistor. The first light emission control transistor includes a gate electrode for receiving a light emission control signal, and is configured to turn on upon receiving the light emission control signal to determine a timing of flow of a driving current to the organic light-emitting diode, and is a PMOS transistor. The driving transistor is connected to the switching transistor and the first light emission control transistor and provides the driving current to the organic light-emitting diode.

A semiconductor device with favorable electrical characteristics, a semiconductor device with stable electrical characteristics, or a highly reliable semiconductor device or display device is provided. A first insulating layer and a first conductive layer are stacked over a first region of a first metal oxide layer. A first layer is formed in contact with a second metal oxide layer and a second region of the first metal oxide layer that is not overlapped by the first insulating layer. Heat treatment is performed to lower the resistance of the second region and the second metal oxide layer. A second insulating layer is formed. A second conductive layer electrically connected to the second region is formed over the second insulating layer. Here, the first layer is formed to contain at least one of aluminum, titanium, tantalum, and tungsten.

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.