An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.

An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se.

Provided is a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element has a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated. The solid-state imaging element includes a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate, and a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, where the light-blocking metal film has an opening opened so as to allow the through electrode to pass through. The solid-state imaging element further includes a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side.

The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving sensitivity while suppressing deterioration of color mixing. The solid-state imaging device includes a substrate, a first photoelectric conversion region in the substrate, a second photoelectric conversion region in the substrate, a trench between the first photoelectric conversion region and the second photoelectric conversion region and penetrates through the substrate, a first concave portion region that has a plurality of concave portions provided on a light receiving surface side of the substrate, above the first photoelectric conversion regions, and a second concave portion region that has a plurality of concave portions provided on the light receiving surface side of the substrate, above the second photoelectric conversion region. The technology of the present disclosure can be applied to, for example, a backside illumination solid-state imaging device and the like.

A back-illuminated semiconductor light detecting device includes a light detecting substrate having pixels, and a circuit substrate having signal processing units. For each of the pixels, the light detecting substrate includes avalanche photodiodes respectively having light receiving regions provided in a first main surface side of the semiconductor substrate. In the semiconductor substrate, for each pixel, a trench surrounds at least one region including the light receiving region when viewed from a direction perpendicular to the first main surface. The number of signal processing units is larger than the number of light receiving regions in each pixel, and the number of regions surrounded by the trench in each pixel is equal to or less than the number of light receiving regions in the pixel.

The present disclosure provides an active pixel sensing circuit structure, an active pixel sensor, a display penal and a display device, aiming to reduce an area of the active pixel sensing circuit structure. A control electrode of a second transistor in the active pixel sensing circuit structure is located in a first metal layer. A first voltage signal line, a second voltage signal line, and an output signal line are located in a second metal layer that is located on a side of the first metal layer facing away from the substrate. A first electrode of a photodiode is connected to the control electrode of the second transistor through a first connection line. The first connection line is located in a third metal layer that is located on a side of the second metal layer facing away from the substrate.

A Light Detection And Ranging (LIDAR) measurement circuit includes a control circuit configured to receive respective detection signals output from one or more single-photon detectors in response to a plurality of photons incident thereon. The control circuit includes a photon counter circuit including a digital counter circuit and an analog counter circuit, the digital counter circuit being responsive to an output of the analog counter circuit or the analog counter circuit being responsive to an output of the digital counter circuit to count detection of respective photons of the plurality of photons based on the respective detection signals, and a time integration circuit configured to output a time integration signal representative of respective times of arrival indicated by the respective detection signals. The control circuit is configured to calculate an estimated time of arrival of the plurality of photons based on a ratio of the time integration signal and the count of the detection of the respective photons of the plurality of photons.

There is provided a pixel circuit including a first circuit and a second circuit. The first circuit is used to output a first voltage associated with exposure intensity. The second circuit is used to output a second voltage associated with exposure time interval. The processor multiples the first voltage to a ratio between a reference voltage and the second voltage to obtain an actual light intensity, wherein the reference voltage is a voltage value outputted by the second circuit of a dummy pixel.

A photoelectric conversion device includes a first pixel including a photoelectric converter, a first node to which charge is transferred from the photoelectric converter, and a first transistor that resets a voltage of the first node, and configured to output a first signal in accordance with a voltage of the first node, a second pixel including a second node to which a predetermined voltage is supplied and a second transistor that resets a voltage of the second node, and configured to output a second signal in accordance with a voltage of the second node; and a control line connected to the first transistor and the second transistor. The first transistor resets the first node to a first voltage, and the second transistor resets the second node to a second voltage having a smaller amplitude than the first voltage.