A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Disclosed herein is a phototransistor (PT) comprising an emitter, a collector and a floating base; wherein the floating base, a p-n junction between the emitter and base (E-B junction) and a p-n junction between the base and the collector (B-C junction) are collectively in direct physical contact only with and completely encapsulated only by the emitter, the collector, and a section of a dielectric. Under an operating condition of the PT, a DC current density averaged over the E-B junction or a DC current density averaged over the B-C junction may be at least 100 times of a DC current density averaged over an opto-electronically active region of the PT. A sum of a capacitance of the E-B junction and a capacitance of the B-C junction may be less than 1 fF.

Provided is a display device or a display system capable of displaying images along a curved surface, a display device or a display system capable of displaying images seamlessly in the form of a ring, or a display device or a display system that is suitable for increasing in size. The display device includes a display panel. The display panel includes a first part and a second part and is flexible. The first part can display images. The second part can transmit visible light. The display panel is curved so that the second part and the first part overlap with each other.

A microfluidic device can include a base an outer surface of which forms one or more enclosures for containing a fluidic medium. The base can include an array of individually controllable transistor structures each of which can comprise both a lateral transistor and a vertical transistor. The transistor structures can be light activated, and the lateral and vertical transistors can thus be photo transistors. Each transistor structure can be activated to create a temporary electrical connection from a region of the outer surface of the base (and thus fluidic medium in the enclosure) to a common electrical conductor. The temporary electrical connection can induce a localized electrokinetic force generally at the region, which can be sufficiently strong to move a nearby micro-object in the enclosure.

An optical apparatus including a semiconductor substrate; a first light absorption region supported by the semiconductor substrate, the first light absorption region including germanium and configured to absorb photons and to generate photo-carriers from the absorbed photons; a first layer supported by at least a portion of the semiconductor substrate and the first light absorption region, the first layer being different from the first light absorption region; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, wherein the second control signal is different from the first control signal.

Disclosed are a semiconductor photodiode (PD) or phototransistor (PT) photo detector with a unipolarly doped edge region containing a portion of the photon absorption layer and occupying over 99% of the photo detector area as projected on a plane parallel to the semiconductor substrate. Embodiments also relate to methods of making the photo detector.

The present application concerns an optical sensor that includes one or more charge transfer pixels (10) each including a buried photodiode (11) generating a photoelectric charge when illuminated, a conversion element (12) receiving at least a portion of the photoelectric charge and tending to impose, on the photodiode, a potential satisfying a non-linear relationship with the intensity of generation of the photoelectric charge, and a charge transfer element (14) for reading the charge stored by the photodiode (11) such that the residual charge in same is zero after the reading by transfer.

An image sensor circuit, comprises: a photo sensing circuit including a photo sensitive device for sensing a light signal to generate a photo sensing signal at a photo sensing output node; a charge storage device, coupled to an integration node; an integration switch coupled between the photo sensing output node and the integration node, operating according to an integration control signal; and a reset circuit coupled between a voltage supply and the integration node, operating according to a reset control signal and a read control signal, wherein the integration node includes an integration voltage. In a reset time period, the integration switch is conductive, and the reset circuit generates a reset signal on the integration node to bias the photo sensitive device through the integration switch to an active state and to charge the charge storage device such that the integration voltage is determined to be at a reset level.

An avalanche diode arrangement (10) comprises an avalanche diode (11) that is coupled to a first voltage terminal (16) and to a first node (13), an event detector (14) for detecting a trigger event of the avalanche diode (11) and being coupled to the first node (13), a quenching circuit (15) that is coupled to the first node (13), and a detection circuit (20) coupled to the first node (13). The detection circuit (20) is configured to provide a detection signal (SVC2) that depends on a value of a node voltage (SVA) at the first node (13).