A capacitor includes a silicon substrate, a conductor layer, and a dielectric layer. The silicon substrate has a principal surface including a capacitance generation region and a non-capacitance generation region. The silicon substrate includes a porous part provided in a thickness direction in the capacitance generation region. The conductor layer includes a surface layer part at least covering part of a surface of the capacitance generation region and a filling part filled in at least part of the porous part. The dielectric layer is provided between an inner surface of the porous part and the filling part. The porous part includes a macroporous part having macro pores and a nanoporous part formed in at least part of inner surfaces of the macro pores and having nano pores smaller than the macro pores.

Embodiments of the present invention provides a semiconductor device including a reservoir capacitor capable of increasing the surface area of the capacitor by disposing a first electrode having a pillar shape between a substrate and a second electrode and a method for fabricating the same. According to an embodiment of the present invention, the reservoir capacitor comprises: a substrate; a first electrode having a pillar shape and disposed over the substrate; a first dielectric layer disposed between the substrate and the first electrode; a second electrode disposed over the substrate and the first electrode and covering a side surface and a top surface of the first electrode; a second dielectric layer disposed between the first electrode and the second electrode; and a third dielectric layer disposed between the substrate and the second electrode.

The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

A semiconductor device including a substrate and a capacitor is provided. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The first electrode has a plurality of hemispherical recesses. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. Surfaces of the hemispherical recesses are in direct contact with the insulating layer.

Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.

A semiconductor structure, a preparation method of the same, and a semiconductor device are provided. The semiconductor structure includes a substrate, including an active area. A first electrode layer is arranged on the substrate and electrically connected to the active area. The first electrode layer extends in a direction perpendicular to the substrate. A dielectric layer is arranged on a surface of the first electrode layer. A second electrode layer is arranged on a surface of the dielectric layer. Each of the surface of the first electrode layer and the surface of the dielectric layer are provided with an uneven structure.

A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.

A fingerprint sensor includes: a base substrate including a plurality of pixel regions; a sensing dielectric structure formed on the base substrate in the pixel regions; and a sensing connection structure formed in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure and the sensing connection structure is connected to the base substrate. The fingerprint sensor further includes a plurality of electrode plates formed on surfaces of the sensing dielectric structure and the sensing connection structure. A plurality of protrusions are formed on surfaces of the electrode plates. The fingerprint sensor further includes an insulation medium structure formed on the plurality of electrode plates.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.