A switched-capacitor DC-to-DC converter includes a first P-channel MOS transistor, a first N-channel MOS transistor, a second P-channel MOS transistor, and a second N-channel MOS transistor which are connected in series. Drain terminals of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other through a first node, and drain terminals of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other through a second node. A capacitor is coupled between the first and second nodes. The capacitor includes a first capacitor and a second capacitor which are coupled in parallel between the first and second nodes.

Embodiments herein relate to systems, apparatuses, or processes directed to packages that include one or more glass cores that have thin film capacitors on one or more sides of the one or more glass cores. The film capacitors may be formed in-situ on the glass cores during substrate manufacturing. Other embodiments may be described and/or claimed.

Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.

A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.

Capacitors based on stacks of nanoribbons and associated devices and systems are disclosed. In particular, a stack of at least two nanoribbons may be used to provide a two-terminal device referred to herein as a “nanoribbon-based capacitor,” where one nanoribbon serves as a first capacitor electrode and another nanoribbon serves as a second capacitor electrode. Using portions of nanoribbon stacks to implement nanoribbon-based capacitors could provide an appealing alternative to conventional capacitor implementations because it would require only modest process changes compared to fabrication of nanoribbon-based FETs and because nanoribbon-based capacitors could be placed close to active devices. Furthermore, with a few additional process steps, nanoribbon-based capacitors may, advantageously, be extended to implement other circuit blocks such as nanoribbon-based BJTs or three-nanoribbon arrangements with a common connection between two anodes and a separate connection to a cathode.

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.

A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.