A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.

A semiconductor structure and a method for manufacturing same. The semiconductor structure includes: a semiconductor base, including a logical device region and a memory region; a bit line located in the memory region and an electrical contact layer located in the logical device region, which are disposed in a same layer; a first semiconductor channel located on the bit line and a second semiconductor channel located on the electrical contact layer, which are disposed in a same layer; a word line and a gate disposed in a same layer; a capacitor structure, in contact with a second doped region of the first semiconductor channel; an electrical connection structure, in contact with the fourth doped region of the second semiconductor channel; and a dielectric layer, located between the bit line and the word line, and on a side of the word line away from the semiconductor base.

A method according to an embodiment is for forming a capacitor structure on a wafer. A first capacitor is formed on a first side of a wafer, and a second capacitor is formed on a second side of the wafer. The capacitor structure includes the first capacitor and the second capacitor. A trench capacitor is fabricated at both ends of an interposer, which can increase capacitance, and greatly improve the stability of the supplied power.

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

A semiconductor device may include a word line stack over a substrate; a plurality of supporters including vertically extending blocking spacers to support the word line stack; and storage nodes of a capacitor disposed laterally between the supporters.

A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.

A semiconductor device includes bottom electrodes on a substrate. A supporting pattern is disposed between the bottom electrodes in a plan view. A top electrode covers the bottom electrodes and the supporting pattern. A dielectric layer is disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode. A capping pattern is interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer. The capping pattern covers at least a portion of a side surface of the supporting pattern and extends to cover a top surface of the supporting pattern and top surfaces of the bottom electrodes.

The present application discloses a method for fabricating a semiconductor device with a pad structure. The method includes providing a substrate, forming a capacitor structure above the substrate, forming a plurality of passivation layers above the capacitor structure, forming a pad opening in the plurality of passivation layers, performing a passivation process comprising soaking the pad opening in a precursor, and forming a pad structure in the pad opening. The precursor is dimethylaminotrimethylsilane or tetramethylsilane. Forming the pad structure in the pad opening comprises forming a pad bottom conductive layer comprising nickel in the pad opening and forming a pad top conductive layer on the pad bottom conductive layer. The pad top conductive layer comprises palladium, cobalt, or a combination thereof.

A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.