A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.

A gate controlled semiconductor device comprising a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region. The device further comprises at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region. The device further comprises at least one active trench extending from a surface into the drift region, in which the at least one first contact region adjoins the at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region. The at least one active trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises different thicknesses; at least one auxiliary trench extending from the surface into the drift region. The at least one auxiliary trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises a constant thickness.

A semiconductor device includes a middle field stop layer having a first conductivity type impurity concentration higher than a drift layer and arranged at a position in the drift layer. A ratio of a depth of the position of the middle field stop layer from a front surface of a semiconductor substrate to a thickness of the semiconductor substrate is equal to or greater than fifteen percent and equal to or less than thirty-five percent. When an IGBT is arranged in the semiconductor device, vibration of a collector voltage waveform in a switching off of the IGBT is restricted. When a diode is arranged in the semiconductor device, vibration of a recovery waveform in a recovery operation of the diode is restricted. Accordingly, at least one of the vibrations of the recovery waveform and the collector voltage waveform in the switching is restricted.

Method for manufacturing an insulated gate bipolar transistor, which includes a drift layer of a first conductivity type between an emitter side, at which a gate and emitter electrode are arranged, and a collector side, at which a collector electrode is arranged including steps: providing a substrate of a second conductivity type, applying a dopant of the first conductivity type on the first side, creating a drift layer of the first conductivity type on the first layer, diffusing the ions such that a buffer layer is created, having a higher doping concentration than the drift layer, creating a base layer of the second conductivity type on the drift layer, creating an emitter layer of the first conductivity type on the base layer, thinning the substrate on the second side such that the remaining part of the substrate forms a collector layer.

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

In an embodiment, a process of forming an electronic device can include providing a semiconductor substrate having a first major side and an electronic component at least partly within the semiconductor substrate along the first major side; The process can further include thinning the semiconductor substrate to define a second major surface along a second major side opposite the first major side; and selectively removing a portion of the semiconductor substrate along the second major side to define a trench having a distal surface. The process can further include forming a feature adjacent to or within the trench. The feature can include a doped region, a conductive structure, or the like. In another embodiment, an electronic device can include the semiconductor substrate and a conductive structure within a trench. The conductive layer can laterally surround a pillar within the trench.

Provided is a switch apparatus including a conductor; a switching device that contacts the conductor on a first surface and switches between a first terminal on the first surface side and a second terminal on a second surface side that is opposite to the first surface; and a control device that contacts the conductor on a third surface and includes a control circuit of the switching device provided on a fourth surface side opposite to the third surface and a first withstand voltage structure that protects the control circuit from excessive voltage added to the conductor. By providing the withstand voltage structure in the control device, it is possible to protect the control circuit.