A semiconductor device includes a third electrode between a first semiconductor region and a second electrode, a fourth electrode between the first semiconductor region and the second electrode, a second semiconductor region between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth electrode between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and a fifth semiconductor region between the first electrode and the first semiconductor region. A first insulating film is provided between the third electrode and the first semiconductor region, the second semiconductor region, the third semiconductor region and the second electrode. A second insulating film is provided between the fourth semiconductor region and the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n.sup.− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p.sup.+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n.sup.+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×10.sup.15 cm.sup.−3 or more, and one-tenth or less of the peak impurity concentration of the p.sup.+ type collector layer, can be included between the n-type field-stop layer and p.sup.+ type collector layer.

There are disclosed herein various implementations of a bipolar semiconductor device with multi-trench enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having an opposite, second conductivity type. The device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region and extends from the first control trench to the first second depletion trench and further from the first depletion trench to the second depletion trench.

A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential.

Methods of fabricating ESD protection devices include forming a single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40 V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly-doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40 V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer. The lightly-doped area covers the corner of the heavily-doped area, and the breakdown voltage of a junction between the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer corresponds to the breakdown voltage of a junction between the second semiconductor epitaxial layer and the heavily-doped area.

The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.

Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.

In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.