Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

A semiconductor device which reduces a concentration of the hole current on the upper-surface side. The semiconductor device includes a buffer layer of the first conductivity type, an upper-surface region on the upper-surface side from the buffer layer, and a lower-surface region on the lower-surface side from the buffer layer. A collector layer of the second conductivity type formed in the lower-surface region includes a first collector layer and a second collector layer with impurity concentration lower than that of the first collector layer, these two layers being formed alternately. The upper-surface region includes a first upper-surface region over the first collector layer and a second upper-surface region over the second collector layer. In the first upper-surface region, a hole discharge promoting structure is formed, which promotes hole discharge from the top of the first collector layer.

Provided is field-effect transistor structure including: a substrate including therein at least one 1.sup.st doped region, a 2.sup.nd doped region on one side of the 1.sup.st doped region, and a 3.sup.rd doped region on another side of the 1.sup.st doped region; a 1.sup.st channel structure including therein a 4.sup.th doped region on the 2.sup.nd doped region in the substrate; and a 2.sup.nd channel structure, at a side of the 1.sup.st channel structure, including therein a 5.sup.th doped region on the 3.sup.rd doped region in the substrate, wherein the 4.sup.th, 2.sup.nd, 1.sup.st, 3.sup.rd and 5.sup.th doped regions form a sequentially connected passive device.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

Embodiments of the disclosure provide a lateral bipolar transistor on a semiconductor fin and methods to form the same. A bipolar transistor structure according to the disclosure may include a doped semiconductor layer coupled to a base contact. A first semiconductor fin on the doped semiconductor layer may have a first doping type. An emitter/collector (E/C) material may be on a sidewall of an upper portion of the first semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.