The present invention relates to a method of manufacturing an AlN-based transistor. An AlN-based high electron mobility transistor (HEMT) element according to the present invention may use an AlN buffer layer, and include an AlGaN composition change layer inserted into a GaN/AlN interface to remove or suppress a degree of generation of a two-dimensional hole gas (2DHG), thereby decreasing an influence of a coulomb drag on a two-dimensional electron gas (2DEG) layer and improving mobility of a two-dimensional electron gas (2DEG).

Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including Si.sub.xGe.sub.1−x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including Si.sub.xGe.sub.1−x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.

A semiconductor device includes a substrate, a buffer layer including a nitride semiconductor and formed over the substrate, a composition gradient layer including a nitride semiconductor and formed over the buffer layer, a first semiconductor layer including a nitride semiconductor and formed over the composition gradient layer, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer. The buffer layer is formed of a material including GaN, the composition gradient layer is formed of a material including Al, and the proportion of Al in the composition gradient layer increases from a first side of the composition gradient layer closer to the buffer layer toward a second side of the composition gradient layer closer to the first semiconductor layer.

The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.

An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.

An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.