In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels in a gate of a transistor. The use of multiple nanowires as channels allows for different V.sub.t (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric layer) that surrounds each of the nanowire channels. Memory window is about 2d (thickness of a fe layer). Setting voltage is also proportional to the fe layer thickness. The V.sub.t of the device is the superposition of the various fe layers. For example, if there are three channels with three different Fe layer (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels in the device.

An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Transistors with switchable polarity and non-volatile configurations are provided. The transistors include a van der Waals (vdW) semiconductor layer. A ferroelectric layer with local polarization determines the type and concentration of the doping in the vdW semiconductor layer. Local program gates allow application of voltage to set or switch the polarization in the ferroelectric layer in the source and drain regions. Source and drain contacts permit either n-type or p-type transistor operations according to the carrier polarity in the vdW semiconductor layer.

Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

Provided are a thin film structure, a semiconductor device including the thin film structure, and a semiconductor apparatus including the semiconductor device. The thin film structure includes a substrate, and a ferroelectric layer on the substrate. The ferroelectric layer includes a compound having fluorite structure, in which a <001> crystal direction is aligned in a normal direction of a substrate, and having an orthorhombic phase and including fluorine. The ferroelectric layer may have ferroelectricity.

Disclosed is a method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film. The method includes forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate, forming channel holes penetrating the mold structure, forming vertical channel structures inside the channel holes, forming an isolation trench penetrating the mold structure and having a line shape extending in one direction, selectively removing the sacrificial layers exposed by the isolation trench, forming gate electrodes filling a space from which the sacrificial layers are removed, and performing a heat treatment process and a cooling process for the vertical channel structures.