A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.

A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.

Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.

A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.