A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.

An ESD Protection Device includes a semiconductor body including a substrate, conductivity regions, and emitter and collector portions. Laterally adjacent first and second conductivity regions are arranged at least partially within the semiconductor body. The emitter and collector portions are disposed in contact with and arranged over the first and second conductivity regions respectively. The third conductivity region is disposed between the second conductivity region and the collector portion. The first and third conductivity regions have a first conductivity type. The second conductivity region, and the emitter and collector portions have a second conductivity type different from the first conductivity type. When an electrostatic discharge level exceeds a predetermined level, a first discharge current passes between the emitter portion and the collector portion through the first and second conductivity regions. A second discharge current subsequently occurs and passes between the first and third conductivity regions through the second conductivity region.

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a gate region, and an active region arranged adjacent to the gate region in a horizontal direction. A first emitter, a first base, and a second base are arranged consecutively between the second and first surfaces in a vertical direction. A front-facing emitter is arranged in the active region and extends in the vertical direction from the first surface to the second base. Short-circuit regions extend from the first surface through the front-facing emitter to the second base. The active region has, in the horizontal direction, a first edge region adjacent to the gate region, a failure region adjacent to the first edge region, and a second edge region adjacent to the failure region. An average density of the short-circuit regions in the failure region is lower than in both edge regions.

A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

A light emitting component includes: plural transfer devices that successively come into ON state; plural setting thyristors that are connected to the plural transfer devices, respectively, and come into a state of being able to shift to ON state by the transfer devices coming into ON state; and plural light emitting devices that are connected to the plural setting thyristors in series, respectively, and emit light or increase in light emission amounts when the setting thyristors come into ON state, and the setting thyristors are formed so as to comprise a voltage reducing layer having a bandgap smaller than bandgaps of light emitting layers of the light emitting devices.

The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 m from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.