Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.

A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

A display apparatus including color filters is disclosed. The display apparatus may comprise a device substrate including pixel areas. A light-emitting device may be disposed on each pixel area. An encapsulating layer covering the light-emitting devices may be disposed on the device substrate. The color filters may be disposed on the encapsulating layer. For example, separating dams defining openings overlapping with the light-emitting devices may be disposed on the encapsulating layer. The pixel areas disposed in a first direction may display the same color. Some of the separating dams extending in a second direction that is different from the first direction between the pixel areas may have a relatively short length. Thus, in the display apparatus, the volume difference between the color filters may be reduced.

Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.

Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

A semiconductor device structure and a formation method are provided. The semiconductor device structure includes a stack of channel structures and includes a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes a dielectric fin stacked over an isolation structure. The dielectric fin is adjacent to the second epitaxial structure, and the isolation structure is adjacent to the backside conductive contact. The isolation structure has a first height, the dielectric fin has a second height, and the second height is greater than the first height.

A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.