Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

Bidirectional thyristor device comprising a semiconductor body extending in a vertical direction between a first main surface and a second main surface opposite the first main surface, a first main electrode arranged on the first main surface, and a second main electrode arranged on the second main surface, is specified, wherein the semiconductor body comprises a first base layer of a first conductivity type, a second base layer of the first conductivity type, and a third base layer of a second conductivity type different than the first conductivity type arranged between the first base layer and the second base layer. The first main electrode acts as a cathode for a first thyristor functional element and as an anode for a second thyristor functional element of the bidirectional thyristor device. The bidirectional thyristor device is configured asymmetrically with respect to the first thyristor functional element and the second thyristor functional element.

A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

In a light emitting element array in which a plurality of components having multiple light emitting thyristors connected to a single shift thyristor are arranged in a plurality of lines, the density of the light emitting thyristor is increased without reduction in the amount of light emission of each of the light emitting thyristors. In the light emitting element array in which multiple light emitting thyristors are formed on a single island structure and the multiple light emitting thyristors are connected to a single shift thyristor, a first element-isolating groove that element-isolates the multiple light emitting thyristors from each other inside the single island structure is formed shallower than a second element-isolating groove that element-isolates the island structure.

A thyristor is formed from a vertical stack of first, second, third, and fourth semiconductor regions of alternated conductivity types. The fourth semiconductor region is interrupted in a gate area of the thyristor. The fourth semiconductor region is further interrupted in a continuous corridor that extends longitudinally from the gate area towards an outer lateral edge of the fourth semiconductor region. A gate metal layer extends over the gate area of the thyristor. A cathode metal layer extends over the fourth semiconductor region but not over the continuous corridor.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a gate region, and an active region arranged adjacent to the gate region in a horizontal direction. A first emitter, a first base, and a second base are arranged consecutively between the second and first surfaces in a vertical direction. A front-facing emitter is arranged in the active region and extends in the vertical direction from the first surface to the second base. Short-circuit regions extend from the first surface through the front-facing emitter to the second base. The active region has, in the horizontal direction, a first edge region adjacent to the gate region, a failure region adjacent to the first edge region, and a second edge region adjacent to the failure region. An average density of the short-circuit regions in the failure region is lower than in both edge regions.

A power diode comprises a plurality of diode cells (10). Each diode cell (10) comprises a first conductivity type first anode layer (40), a first conductivity type second anode layer (45) having a lower doping concentration than the first anode layer (40) and being separated from an anode electrode layer (20) by the first anode layer (40), a second conductivity type drift layer (50) forming a pn-junction with the second anode layer (45), a second conductivity type cathode layer (60) being in direct contact with the cathode electrode layer (60), and a cathode-side segmentation layer (67) being in direct contact with the cathode electrode layer (30). A material of the cathode-side segmentation layer (67) is a first conductivity type semiconductor, wherein an integrated doping content of the cathode-side, which is integrated along a direction perpendicular to the second main side (102), is below 2.Math.10.sup.13 cm.sup.?2, or a material of the cathode-side segmentation layer (67) is an insulating material. A horizontal cross-section through each diode cell (10) along a horizontal plane (K1) comprises a first area where the horizontal plane (K1) intersects the second anode layer (45) and a second area where the plane (K1) intersects the drift layer (50).

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

In a light emitting element array in which a plurality of components having multiple light emitting thyristors connected to a single shift thyristor are arranged in a plurality of lines, the density of the light emitting thyristor is increased without reduction in the amount of light emission of each of the light emitting thyristors. In the light emitting element array in which multiple light emitting thyristors are formed on a single island structure and the multiple light emitting thyristors are connected to a single shift thyristor, a first element-isolating groove that element-isolates the multiple light emitting thyristors from each other inside the single island structure is formed shallower than a second element-isolating groove that element-isolates the island structure.