A method of fabricating semiconductor-superconductor nanowires, comprising: forming a first mask amorphous mask having first openings over trenches in a substrate; forming a monocrystalline conducting material in the first openings by selective area growth, thus forming gates for the nanowires in the trenches pf the substrate; forming a second mask over the substrate and gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer in the second openings; forming a crystalline semiconductor material on the buffer in the second openings by selective area growth in order to form the cores of the nanowires, wherein the gates intersect with the cores in the plane of the substrate; and forming the coating of superconductor material over at least part of each of the cores.

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided, and the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone formed in the substrate adjacent to the first well zone, a gate oxide layer formed on the first well zone and the second well zone, a gate formed on the gate oxide layer, an insulation region formed on the surface of the second well zone, a first implant region formed in the second well zone underneath the insulation region, a second implant region formed below the first implant region, and a junction formed between the first implant region and the second implant region. At least one of the first implant region and the second implant region includes at least two sub-implant regions having different implant concentrations. The sub-implant region having the higher implant concentration is adjacent to the junction.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.

High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, gate-connected field plate, and source-connected field plate.

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

An integrated circuit structure comprises a plurality of structures above a substrate, wherein spacing between the structures creates a range of different open density regions from a relatively low open density region to a high open density region. A first fill material fills at least a portion of openings between the structures in at least the high open density region to provide a substantially uniform open density across the different open density regions, wherein the first fill material is patterned to include openings therein. A second fill material fills the openings between the structures in the low open density region, and fills the openings in the first fill material in the at least the high open density region.

A spin qubit quantum device, comprising: a semiconductor portion comprising a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, and wherein the first gate is not aligned with the second gates.