A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.

There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same. According to an embodiment, the semiconductor device may include a vertical active region disposed on a substrate and comprising a first source/drain layer, a channel layer and a second source/drain layer which are stacked in sequence; a gate stack surrounding at least a part of a periphery of the channel layer; and at least one of: a first electrical connection component for the first source/drain layer, comprising a first contact portion disposed above a top surface of the active region and a first conductive channel in contact with the first contact portion and extending from the top surface of the active region to be in contact with at least a part of sidewalls of the first source/drain layer; and a second electrical connection component for the gate stack, comprising a second contact portion disposed above the top surface of the active region and a second conductive channel in contact with the second contact portion and extending from the top surface of the active region to be in contact with at least a part of sidewalls of a gate conductor layer in the gate stack.

A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

[Problem] To improve the drain current ON/OFF ratio characteristics. [Solution] A tunnel field-effect transistor 10 of the present invention is such that, when the gate length is denoted by L.sub.G and the extension distance of a source region 1 extended toward a drain region 3 from a position in the source region 1 is denoted by L.sub.OV, L.sub.TG expressed in Formula (1) below as the shortest distance between the position of an extension end of the source region 1 based on a drain-side reference position as the side face position of a gate electrode 6a, 6b closest to the drain region 3, and the position in the semiconductor layer 4 opposite to the drain-side reference position in the height direction of the gate electrode 6a, 6b satisfies a condition of Inequality (2) below. Note that l.sub.t_OFF in Inequality (2) denotes a shortest tunnel distance over which carriers move from the source region to a channel region through a tunnel junction surface in an OFF state of the tunnel field-effect transistor.

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided, and the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip. Moreover, the charging and discharging (writing/erasing), as well as the reading voltages are lower than those needed for CMOS based flash memory cells, due to the small nano-Schottky contact (301) and the small size of the nanoparticle for charge storage.

A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.