A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer (203) on an upper surface of a device (S1); implanting silicon ions and/or indium ions in a region of the first dielectric layer (203) corresponding to an ohmic contact electrode region, and in the ohmic contact electrode region of the device (S2); growing a second dielectric layer (206) on an upper surface of the first dielectric layer (203) (S3); activating the silicon ions and/or the indium ions by means of a high temperature annealing process, so as to form an N-type heavy doping (S4); respectively removing portions, corresponding to the ohmic contact electrode region, of the first dielectric layer (203) and the second dielectric layer (206) (S5); growing a metal layer (208) on the upper surface of the ohmic contact electrode region of the device, so as to form an ohmic contact electrode (S6). The ohmic contact electrode prepared by the method can ensure that the metal layer (208) has flat surfaces, smooth and regular edges, and said electrode has stable device breakdown voltage, and is reliable and has a long service life.

To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

An object of the present invention is to shorten the switching delay time of a semiconductor device.

Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.

Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate. The vertical FET comprises a lower source/drain region disposed on the substrate. The lower source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface, wherein the bottom surface of the lower source/drain region contacts the substrate. A lower metallic contact is disposed adjacent to, and in contact with, at least one sidewall surface of the lower source/drain region, wherein the lower metallic contact comprises a laterally extended portion which laterally extends from the at least one sidewall surface of the lower source/drain region. A vertical source/drain contact is disposed adjacent to the vertical FET device and contacts the laterally extended portion of the lower metallic contact.

Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

A semiconductor device includes: a trench; a first electrode is formed in the trench; a first impurity region, which has a first conductivity type and is formed to abut on the trench; a second impurity region, which has a second conductivity type and is formed to abut the trench; an insulating film, which is formed on the front surface of the semiconductor substrate; a conductive plug, which is formed to penetrate through the insulating film and is electrically connected to the first impurity region and the second impurity region; wherein the conductive plug includes: a silicon layer made of silicon other than a single crystal; a silicide crystallite contained in the silicon layer; and a blocking layer that is formed to cover sides of the silicon layer and is made of a material that is impervious to the silicide crystallites.

A method is described for forming at least one metal contact on a surface of a semiconductor and a device with at least one metal contact. The method is used for forming at least one metal contact (60) on a surface (11) of a semiconductor (10) and has the steps of: applying a metal layer (20) of palladium onto the semiconductor surface (11), applying a mask (40, 50) onto the metal layer (20), and structuring the palladium of the metal layer (20) using the mask (40, 50), wherein lateral deposits (21) of the metal are formed on sidewalls of the mask by the structuring so that the mask is embedded between the deposits (21) and the structured metal layer (20′) after the structuring. Since the mask is conductive, it can remain embedded in the metal. The deposits and the mask form a part of the contact.

A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region. A difference between a concentration of an n-type impurity and the concentration of the p-type impurity in the n-type semiconductor region is not less than 1.0×10.sup.19 cm.sup.−3.

Certain embodiments provide a semiconductor device of an example including a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, a drain electrode and source electrode provided on the semiconductor layer, a gate electrode provided between the drain electrode and the source electrode on the semiconductor layer, and a heat transfer unit provided so as to fill a groove which penetrates the semiconductor layer right below the drain electrode till reaches the semiconductor substrate. The heat transfer unit includes a material different from that of the drain electrode and having thermal conductivity higher than that of the semiconductor substrate and the semiconductor layer under an operating temperature of the semiconductor device.