A semiconductor device includes a semiconductive substrate, a semiconductive fin, an isolation structure, a source/drain epitaxial structure, a first cap layer, and a second cap layer. The semiconductive fin protrudes from the semiconductive substrate. The isolation structure is over the semiconductive substrate and laterally surrounds the semiconductive fin. The source/drain epitaxial structure is over the semiconductive fin. The source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner. The first cap layer extends from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure. The second cap layer covers the rounded corner and a bottom of the source/drain epitaxial structure. The first and second cap layers are made of different materials.

Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.

A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization.

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

A method includes forming a first semiconductor fin on a substrate, forming a source/drain region in the first semiconductor fin, depositing a capping layer on the source/drain region, where the capping layer includes a first boron concentration higher than a second boron concentration of the source/drain region, etching an opening through the capping layer, the opening exposing the source/drain region, forming a silicide layer on the exposed source/drain region and forming a source/drain contact on the silicide layer.

Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

A modular guided keeper base, guided keeper assembly, and related method includes a modular guided keeper base that mounts to a die member. The guided keeper base has an integrated stop for guide pin retention. The guided keeper base can also accommodate a variety of bushings within the base. The guided keeper base is attached to a die member using a mounting flange(s). Mounting fasteners pass through the fastener holes in the mounting flanges and are anchored in the die member to securely retain the guided keeper assembly in place. A retainer ring is mounted in an associated groove in the base over the heads of the mounting fasteners to prevent unintentional unfastening of the fasteners from the die member.

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.