Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): $\begin{array}{cc}{d}_g\sqrt{\frac{2E_{F}q\left(N_{\mathrm{DA}}+N_A-N_{\mathrm{DD}}-N_D\right)}{{\epsilon }_0{\epsilon }_C}}+{\Phi }_B-\frac{d_{B}P}{{\epsilon }_0{\epsilon }_C}>0.& \left(1\right)\end{array}$

A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.

Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate lever 15, and satisfying the following formula (1): $\begin{array}{c}{d}_G\sqrt{\frac{2E_{F}q\left(N_{\mathrm{DA}}+N_A-N_{\mathrm{DD}}-N_D\right)}{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_C}}+{\Phi }_B-\frac{d_{B}P}{{\mathrm{.Math.}}_0}\end{array}$

A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.

A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.

A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.

Included are forming, on a semiconductor substrate, an insulation film having an opening section where an opening is formed, forming a first resist on the insulation film while avoiding the opening section and the semiconductor substrate exposed via the opening section, forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method, removing, by a lift-off method, the first resist and the first metal on the first resist, forming, on the insulation film, a second resist allowing the first metal to be exposed, causing the first metal to grow a second metal by an electroless plating method, and removing the second resist, where these processings are included in the listed order.

A semiconductor device manufacturing method includes: forming an electrode including an Ni layer and an Au layer successively stacked on a semiconductor layer; forming a Ni oxide film by performing heat treatment to the electrode at a temperature of 350° C. or more to deposit Ni at least at a part of a surface of the Au layer and to oxidize the deposited Ni; and forming an insulating film in contact with the Ni oxide film and containing Si.