A display device includes a first transistor. The first transistor includes an oxide semiconductor layer, a first gate electrode facing the oxide semiconductor layer and a gate insulating layer between the oxide semiconductor layer and the first gate electrode. The first gate electrode has hydrogen storage properties.

A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

An integrated circuit (IC) device, and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure at a first lateral end of the multilayer stack; an epitaxial drain structure at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers between the gate structure and respective ones of the source structure and the drain structure, wherein at least one of the source structure or the drain structure does not exhibit a pattern of crystallographic defects extending from the inner spacers.

A semiconductor device includes a lower nano device that includes a plurality of stacked first nano sheets, where the first nano sheets are spaced apart from each other a first distance. An upper nano device that includes a plurality of stacked second nano sheets, where the second nano sheets are spaced apart from each other a second distance, where the second distance is larger than the first distance.

A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.

Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.

The present application relates to an active switch, a manufacturing method thereof and a display device. The manufacturing method of the active switch includes: sequentially forming a gate electrode, a gate insulating layer, an active layer, a semiconductor composite layer and a source electrode and a drain electrode on a substrate. The semiconductor composite layer includes a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer and a second N-type lightly doped amorphous silicon layer which are sequentially stacked, where the ion doping concentration of the first N-type heavily doped amorphous silicon layer is lower than that of the second N-type heavily doped amorphous silicon layer, and the ion doping concentration of the first N-type lightly doped amorphous silicon layer is higher than that of the second N-type lightly doped amorphous silicon layer.

Described herein are low temperature processed high quality silicon containing films. Also disclosed are methods of forming silicon containing films at low temperatures. In one aspect, there are provided silicon-containing film having a thickness of about 2 nm to about 200 nm and a density of about 2.2 g/cm.sup.3 or greater wherein the silicon-containing thin film is deposited by a deposition process selected from a group consisting of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), cyclic chemical vapor deposition (CCVD), plasma enhanced cyclic chemical vapor deposition (PECCVD, atomic layer deposition (ALD), and plasma enhanced atomic layer deposition (PEALD), and the vapor deposition is conducted at one or more temperatures ranging from about 25° C. to about 400° C. using an alkylsilane precursor selected from the group consisting of diethylsilane, triethylsilane, and combinations thereof.

Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.